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108 lines
3.2 KiB
Verilog
108 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
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/* latches.v
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Copyright (c) 2015, Stephen J. Leary
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the <organization> nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module latches(
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input clkcpu, // system cpu clock.
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// "wishbone bus" the ack is externally generated currently.
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input wb_cyc,
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input wb_stb,
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input wb_we,
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input [15:2] wb_adr, // la
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input [7:0] wb_dat_i, // bd
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output [7:0] wb_dat_o, // bd
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// floppy latch signals.
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output [3:0] floppy_drive,
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output floppy_side,
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output floppy_motor,
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output floppy_inuse,
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output floppy_density,
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output floppy_reset,
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// place any signals that need to be passed up to the top after here.
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input [4:0] joy0,
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input [4:0] joy1,
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output [1:0] baseclk,
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output [1:0] syncpol
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);
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//reg [7:0] printer_data;
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reg [7:0] ext_latch_a;
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reg [7:0] ext_latch_b;
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reg [7:0] ext_latch_c;
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wire write_request = wb_stb & wb_cyc & wb_we;
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initial begin
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//printer_data = 8'd0;
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ext_latch_a = 8'hFF;
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ext_latch_b = 8'hFF;
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ext_latch_c = 8'd0; // A540 only. Used for VIDC enhancer.
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end
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always @(posedge clkcpu) begin
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if (write_request) begin
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case (wb_adr)
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//14'h0004: printer_data<= wb_dat_i; // 0x10
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14'h0010: ext_latch_a <= wb_dat_i; // 0x40
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14'h0006: ext_latch_b <= wb_dat_i; // 0x18
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14'h0012: ext_latch_c <= wb_dat_i; // 0x48
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endcase
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end
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end
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assign floppy_drive = ext_latch_a[3:0];
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assign floppy_side = ext_latch_a[4];
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assign floppy_motor = ext_latch_a[5];
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assign floppy_inuse = ext_latch_a[6];
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assign floppy_density = ext_latch_b[1];
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assign floppy_reset = ext_latch_b[3];
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assign wb_dat_o = wb_adr == 14'h001e ? {3'b011, joy0} :
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wb_adr == 14'h001f ? {3'b011, joy1} : 8'hFF;
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assign baseclk = ext_latch_c[1:0];
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assign syncpol = ext_latch_c[3:2];
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endmodule
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