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https://github.com/MiSTer-devel/Archie_MiSTer.git
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69 lines
2.6 KiB
Verilog
69 lines
2.6 KiB
Verilog
// ----------------------- i2cSlave_define.v --------------------
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// stream states
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`define STREAM_IDLE 2'b00
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`define STREAM_READ 2'b01
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`define STREAM_WRITE_ADDR 2'b10
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`define STREAM_WRITE_DATA 2'b11
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// start stop detection states
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`define NULL_DET 2'b00
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`define START_DET 2'b01
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`define STOP_DET 2'b10
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// i2c ack and nak
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`define I2C_NAK 1'b1
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`define I2C_ACK 1'b0
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// ----------------------------------------------------------------
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// ------------- modify constants below this line -----------------
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// ----------------------------------------------------------------
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// i2c device address
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`define I2C_ADDRESS 7'h50
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// System clock frequency in MHz
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// If you are using a clock frequency below 24MHz, then the macro
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// for SDA_DEL_LEN will result in compile errors for i2cSlave.v
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// you will need to hand tweak the SDA_DEL_LEN constant definition
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`define CLK_FREQ 32
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// Debounce SCL and SDA over this many clock ticks
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// The rise time of SCL and SDA can be up to 1000nS (in standard mode)
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// so it is essential to debounce the inputs.
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// The spec requires 0.05V of hysteresis, but in practise
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// simply debouncing the inputs is sufficient
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// I2C spec requires suppresion of spikes of
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// maximum duration 50nS, so this debounce time should be greater than 50nS
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// Also increases data hold time and decreases data setup time
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// during an I2C read operation
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// 10 ticks = 208nS @ 48MHz
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`define DEB_I2C_LEN (10*`CLK_FREQ)/48
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// Delay SCL for use as internal sampling clock
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// Using delayed version of SCL to ensure that
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// SDA is stable when it is sampled.
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// Not entirely citical, as according to I2C spec
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// SDA should have a minimum of 100nS of set up time
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// with respect to SCL rising edge. But with the very slow edge
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// speeds used in I2C it is better to err on the side of caution.
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// This delay also has the effect of adding extra hold time to the data
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// with respect to SCL falling edge. I2C spec requires 0nS of data hold time.
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// 10 ticks = 208nS @ 48MHz
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`define SCL_DEL_LEN (10*`CLK_FREQ)/48
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// Delay SDA for use in start/stop detection
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// Use delayed SDA during start/stop detection to avoid
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// incorrect detection at SCL falling edge.
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// From I2C spec start/stop setup is 600nS with respect to SCL rising edge
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// and start/stop hold is 600nS wrt SCL falling edge.
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// So it is relatively easy to discriminate start/stop,
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// but data setup time is a minimum of 100nS with respect to SCL rising edge
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// and 0nS hold wrt to SCL falling edge.
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// So the tricky part is providing robust start/stop detection
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// in the presence of regular data transitions.
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// This delay time should be less than 100nS
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// 4 ticks = 83nS @ 48MHz
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`define SDA_DEL_LEN (4*`CLK_FREQ)/48
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