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47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
//
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// audio.v
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//
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// Archie audio subsystem implementation for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2015 Stephen Leary <stephen@vavi.co.uk>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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module audio(
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input rst,
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input clk, // 32 MHz
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input [15:0] audio_data_r,
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input [15:0] audio_data_l,
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output audio_r,
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output audio_l
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);
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sigma_delta_dac sigma_delta_dac_l (
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.DACout (audio_l),
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.DACin (audio_data_l[15:0]),
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.CLK (clk),
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.RESET (rst)
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);
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sigma_delta_dac sigma_delta_dac_r (
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.DACout (audio_r),
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.DACin (audio_data_r[15:0]),
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.CLK (clk),
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.RESET (rst)
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);
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endmodule |