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https://github.com/MiSTer-devel/Archie_MiSTer.git
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413 lines
8.9 KiB
Verilog
413 lines
8.9 KiB
Verilog
`timescale 1ns / 1ps
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// archimedes_top.v
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//
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// Archimedes top
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//
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// Copyright (c) 2014 Stephen J. Leary <sleary@vavi.co.uk>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module archimedes_top #(parameter CLKCPU)
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(
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// base CPU Clock
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input CLKCPU_I,
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input CLKPIX_I,
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input CEPIX_I,
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output [1:0] SELPIX_O,
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input CEAUD_I,
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input RESET_I,
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// cpu wishbone interface.
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output MEM_CYC_O,
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output MEM_STB_O,
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output MEM_WE_O,
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input MEM_ACK_I,
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input MEM_ERR_I,
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input MEM_RTY_I,
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output [3:0] MEM_SEL_O,
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output [2:0] MEM_CTI_O,
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output [23:2] MEM_ADDR_O,
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input [31:0] MEM_DAT_I,
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output [31:0] MEM_DAT_O,
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// video signals (VGA)
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output HSYNC,
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output VSYNC,
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output [3:0] VIDEO_R,
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output [3:0] VIDEO_G,
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output [3:0] VIDEO_B,
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output VIDEO_EN,
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// VIDC Enhancer selection.
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// These are from external latch C
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output [1:0] VIDBASECLK_O,
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output [1:0] VIDSYNCPOL_O,
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// I2C bus to the CMOS.
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output I2C_DOUT,
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input I2C_DIN,
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output I2C_CLOCK,
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// "Floppy" LED
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output DEBUG_LED,
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// floppy connections to external controller
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input [1:0] img_mounted, // signaling that new image has been mounted
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input img_wp, // write protect. latched at img_mounted
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input [31:0] img_size, // size of image in bytes
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output [31:0] sd_lba,
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output [1:0] sd_rd,
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output [1:0] sd_wr,
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input sd_ack,
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input [7:0] sd_buff_addr,
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input [15:0] sd_buff_dout,
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output [15:0] sd_buff_din,
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input sd_buff_wr,
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// connection to keyboard controller
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output [7:0] KBD_OUT_DATA,
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output KBD_OUT_STROBE,
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input [7:0] KBD_IN_DATA,
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input KBD_IN_STROBE,
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input [4:0] JOYSTICK0,
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input [4:0] JOYSTICK1,
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// audio signal.
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R
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);
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// cpu bus
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wire [31:0] cpu_address;
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wire [3:0] cpu_sel;
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wire cpu_spvmd;
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wire [31:0] cpu_dat_o;
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wire [31:0] cpu_dat_i;
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wire cpu_cyc;
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wire cpu_stb;
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wire cpu_we;
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wire cpu_ack;
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wire cpu_err;
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wire cpu_irq;
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wire cpu_firq;
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// video DMA signals.
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wire [31:0] vid_address; // VIDC D31-D0
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wire vid_flybk; // VIDC FLYBK
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wire vid_req; // VIDC REQ
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wire vid_ack; // VIDC ACK
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wire ioc_cs;
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wire ioc_ack;
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wire [7:0] ioc_dat_o;
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wire rom_low_cs;
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wire [5:0] ioc_cin, ioc_cout;
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a23_core ARM(
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.i_clk ( CLKCPU_I ),
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.o_wb_cyc ( cpu_cyc ),
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.o_wb_stb ( cpu_stb ),
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.o_wb_we ( cpu_we ),
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.o_wb_adr ( cpu_address ),
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.o_wb_sel ( cpu_sel ),
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.i_wb_dat ( cpu_dat_i ),
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.o_wb_dat ( cpu_dat_o ),
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.i_wb_ack ( cpu_ack ),
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.i_wb_err ( cpu_err ),
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.o_wb_tga ( cpu_spvmd ),
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.i_irq ( cpu_irq ),
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.i_firq ( cpu_firq ),
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.i_system_rdy(~RESET_I )
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);
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wire sirq_n;
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wire ram_cs;
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wire vid_we;
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wire snd_ack, snd_req;
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wire [31:0] cpu_dout;
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memc MEMC(
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.clkcpu ( CLKCPU_I ),
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.rst_i ( RESET_I ),
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.spvmd ( cpu_spvmd ),
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// cpu interface
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.cpu_address ( cpu_address[25:0] ),
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.cpu_cyc ( cpu_cyc ),
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.cpu_stb ( cpu_stb ),
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.cpu_we ( cpu_we ),
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.cpu_sel ( cpu_sel ),
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.cpu_ack ( cpu_ack ),
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.cpu_err ( cpu_err ),
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.cpu_dout ( cpu_dout ),
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// memory interface
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.mem_addr_o ( MEM_ADDR_O ),
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.mem_stb_o ( MEM_STB_O ),
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.mem_cyc_o ( MEM_CYC_O ),
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.mem_ack_i ( MEM_ACK_I ),
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.mem_sel_o ( MEM_SEL_O ),
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.mem_we_o ( MEM_WE_O ),
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.mem_cti_o ( MEM_CTI_O ),
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.mem_dat_i ( MEM_DAT_I ),
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// vidc interface
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.hsync ( HSYNC ),
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.flybk ( vid_flybk ),
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.vidrq ( vid_req ),
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.vidak ( vid_ack ),
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.sndak ( snd_ack ),
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.sndrq ( snd_req ),
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.vidw ( vid_we ),
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// ioc interface
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.ioc_cs ( ioc_cs ),
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.rom_low_cs ( rom_low_cs ),
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.ram_cs ( ram_cs ),
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// irqs
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.sirq_n ( sirq_n )
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);
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vidc #(CLKCPU) VIDC
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(
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.clkpix ( CLKPIX_I ),
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.cepix ( CEPIX_I ),
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.selpix ( SELPIX_O ),
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.ceaud ( CEAUD_I ),
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.clkcpu ( CLKCPU_I ),
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.rst_i ( RESET_I ),
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.cpu_dat ( cpu_dat_o ),
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// memc
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.flybk ( vid_flybk ),
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.vidak ( vid_ack ),
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.vidrq ( vid_req ),
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.sndak ( snd_ack ),
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.sndrq ( snd_req ),
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.viddat ( MEM_DAT_I ),
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.vidw ( vid_we ),
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// video signals
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.hsync ( HSYNC ),
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.vsync ( VSYNC ),
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.video_r ( VIDEO_R ),
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.video_g ( VIDEO_G ),
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.video_b ( VIDEO_B ),
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.video_en ( VIDEO_EN ),
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// audio signals
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.audio_l ( AUDIO_L ),
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.audio_r ( AUDIO_R )
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);
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wire [1:0] ioc_speed = cpu_address[20:19];
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wire [7:1] ioc_select;
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wire ioc_sext;
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// podule data bus.
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wire [15:0] pod_dat_o;
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wire [15:0] pod_dat_i;
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wire floppy_firq;
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wire floppy_drq;
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wire ioc_clk2m_en, ioc_clk8m_en;
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ioc IOC(
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.clkcpu ( CLKCPU_I ),
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.clk2m_en ( ioc_clk2m_en ),
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.clk8m_en ( ioc_clk8m_en ),
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.por ( RESET_I ),
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.ir ( vid_flybk ),
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.fh ( {floppy_firq, floppy_drq}),
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.il ( {6'b1111, sirq_n, 1'b1 }),
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.c_in ( ioc_cin ),
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.c_out ( ioc_cout ),
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.select ( ioc_select ),
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.sext ( ioc_sext ),
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// wishbone bus
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.wb_adr ( cpu_address[6:2] ),
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.wb_stb ( cpu_stb & cpu_address[21] & ioc_cs ),
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.wb_cyc ( cpu_cyc & cpu_address[21] & ioc_cs ),
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.wb_we ( cpu_we ),
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.wb_dat_i ( cpu_dat_o[23:16] ),
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.wb_dat_o ( ioc_dat_o ),
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.wb_bank ( cpu_address[18:16] ),
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.irq ( cpu_irq ),
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.firq ( cpu_firq ),
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.kbd_out_data ( KBD_OUT_DATA ),
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.kbd_out_strobe( KBD_OUT_STROBE ),
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.kbd_in_data ( KBD_IN_DATA ),
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.kbd_in_strobe ( KBD_IN_STROBE )
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);
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wire podules_en = ioc_cs & ioc_select[4];
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// all podules live in the the podules module.
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// this is just to keep things tidy.
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podules PODULES(
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// everything is synced to the master 32m clock except the pix clock.
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.clkcpu ( CLKCPU_I ),
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.clk2m_en ( ioc_clk2m_en ),
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.clk8m_en ( ioc_clk8m_en ),
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.rst_i ( RESET_I ),
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.speed_i ( ioc_speed ),
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.wb_cyc ( cpu_cyc & podules_en),
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.wb_stb ( cpu_stb & podules_en),
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.wb_we ( cpu_we & podules_en),
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.wb_dat_o ( pod_dat_o ),
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.wb_dat_i ( cpu_dat_o[15:0] ),
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.wb_adr ( cpu_address[15:2] )
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);
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wire [7:0] floppy_dat_o;
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wire floppy_en = ioc_cs & ioc_select[1];
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// floppy drive signals.
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wire [3:0] floppy_drive;
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wire floppy_side;
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wire floppy_motor;
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wire floppy_inuse;
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wire floppy_density;
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wire floppy_reset;
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fdc1772 #(CLKCPU) FDC1772
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(
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.clkcpu ( CLKCPU_I ),
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.clk8m_en ( ioc_clk8m_en ),
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.wb_cyc ( cpu_cyc & floppy_en),
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.wb_stb ( cpu_stb & floppy_en),
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.wb_we ( cpu_we & floppy_en),
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.wb_dat_o ( floppy_dat_o ),
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.wb_dat_i ( cpu_dat_o[23:16] ),
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.wb_adr ( cpu_address[15:2] ),
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.floppy_firq ( floppy_firq ),
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.floppy_drq ( floppy_drq ),
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.img_mounted ( img_mounted ),
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.img_size ( img_size ),
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.img_wp ( img_wp ),
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.sd_lba ( sd_lba ),
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.sd_rd ( sd_rd ),
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.sd_wr ( sd_wr ),
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.sd_ack ( sd_ack ),
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.sd_buff_addr ( sd_buff_addr ),
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.sd_buff_dout ( sd_buff_dout ),
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.sd_buff_din ( sd_buff_din ),
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.sd_buff_wr ( sd_buff_wr ),
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.floppy_drive ( floppy_drive ),
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.floppy_motor ( floppy_motor ),
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.floppy_inuse ( floppy_inuse ),
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.floppy_side ( floppy_side ),
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.floppy_density( floppy_density ),
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.floppy_reset ( floppy_reset )
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);
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wire [7:0] latches_dat_o;
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wire latches_en = ioc_cs & ioc_select[5] & (ioc_speed == 2'd2);
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latches LATCHES(
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.clkcpu ( CLKCPU_I ),
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.wb_cyc ( cpu_cyc & latches_en ),
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.wb_stb ( cpu_stb & latches_en ),
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.wb_we ( cpu_we & latches_en ),
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.wb_dat_i ( cpu_dat_o[23:16] ),
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.wb_dat_o ( latches_dat_o ),
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.wb_adr ( cpu_address[15:2] ),
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.floppy_drive ( floppy_drive ),
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.floppy_motor ( floppy_motor ),
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.floppy_inuse ( floppy_inuse ),
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.floppy_side ( floppy_side ),
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.floppy_density ( floppy_density ),
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.floppy_reset ( floppy_reset ),
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.joy0 ( JOYSTICK0 ),
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.joy1 ( JOYSTICK1 ),
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.baseclk ( VIDBASECLK_O ),
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.syncpol ( VIDSYNCPOL_O )
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);
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assign MEM_DAT_O = cpu_dat_o;
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assign cpu_dat_i = floppy_en ? {24'd0, floppy_dat_o} :
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latches_en ? {24'd0, latches_dat_o} :
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podules_en ? {16'd0, pod_dat_o} :
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ioc_cs & ~ioc_sext ? {24'd0, ioc_dat_o} :
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ram_cs ? cpu_dout :
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32'hFFFF_FFFF;
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assign I2C_CLOCK = ioc_cout[1];
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assign I2C_DOUT = ioc_cout[0];
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assign ioc_cin[5:0] = {ioc_cout[5:2], I2C_CLOCK, I2C_DIN};
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assign DEBUG_LED = ~(~floppy_inuse & ~floppy_drive[0]);
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endmodule // archimedes_top
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