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207 lines
7.4 KiB
Verilog
207 lines
7.4 KiB
Verilog
//////////////////////////////////////////////////////////////////
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// //
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// Multiplication Module for Amber 2 Core //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// 64-bit Booth signed or unsigned multiply and //
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// multiply-accumulate supported. It takes about 38 clock //
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// cycles to complete an operation. //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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// bit 0 go, bit 1 accumulate
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// Command:
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// 4'b01 : MUL - 32 bit multiplication
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// 4'b11 : MLA - 32 bit multiply and accumulate
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//
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// 34-bit Booth adder
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// The adder needs to be 34 bit to deal with signed and unsigned 32-bit
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// multiplication inputs. This adds 1 extra bit. Then to deal with the
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// case of two max negative numbers another bit is required.
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//
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module a23_multiply (
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input i_clk,
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input i_fetch_stall,
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input [31:0] i_a_in, // Rds
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input [31:0] i_b_in, // Rm
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input [1:0] i_function,
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input i_execute,
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output [31:0] o_out,
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output [1:0] o_flags, // [1] = N, [0] = Z
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output reg o_done
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);
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wire enable;
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wire accumulate;
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wire [33:0] multiplier;
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wire [33:0] multiplier_bar;
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wire [33:0] sum;
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wire [33:0] sum34_b;
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reg [5:0] count = 'd0;
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reg [5:0] count_nxt;
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reg [67:0] product = 'd0;
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reg [67:0] product_nxt;
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reg [1:0] flags_nxt;
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wire [32:0] sum_acc1; // the MSB is the carry out for the upper 32 bit addition
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assign enable = i_function[0];
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assign accumulate = i_function[1];
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assign multiplier = { 2'd0, i_a_in} ;
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assign multiplier_bar = ~{ 2'd0, i_a_in} + 34'd1 ;
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assign sum34_b = product[1:0] == 2'b01 ? multiplier :
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product[1:0] == 2'b10 ? multiplier_bar :
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34'd0 ;
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// Use DSP modules from Xilinx Spartan6 FPGA devices
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`ifdef XILINX_FPGA
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// -----------------------------------
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// 34-bit adder - booth multiplication
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// -----------------------------------
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`ifdef XILINX_SPARTAN6_FPGA
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xs6_addsub_n #(.WIDTH(34))
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`endif
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`ifdef XILINX_VIRTEX6_FPGA
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xv6_addsub_n #(.WIDTH(34))
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`endif
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u_xx_addsub_34_sum (
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.i_a ( product[67:34] ),
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.i_b ( sum34_b ),
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.i_cin ( 1'd0 ),
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.i_sub ( 1'd0 ),
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.o_sum ( sum ),
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.o_co ( )
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);
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// ------------------------------------
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// 33-bit adder - accumulate operations
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// ------------------------------------
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`ifdef XILINX_SPARTAN6_FPGA
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xs6_addsub_n #(.WIDTH(33))
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`endif
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`ifdef XILINX_VIRTEX6_FPGA
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xv6_addsub_n #(.WIDTH(33))
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`endif
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u_xx_addsub_33_acc1 (
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.i_a ( {1'd0, product[32:1]} ),
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.i_b ( {1'd0, i_a_in} ),
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.i_cin ( 1'd0 ),
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.i_sub ( 1'd0 ),
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.o_sum ( sum_acc1 ),
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.o_co ( )
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);
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`else
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// -----------------------------------
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// 34-bit adder - booth multiplication
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// -----------------------------------
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assign sum = product[67:34] + sum34_b;
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// ------------------------------------
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// 33-bit adder - accumulate operations
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// ------------------------------------
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assign sum_acc1 = {1'd0, product[32:1]} + {1'd0, i_a_in};
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`endif
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always @*
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begin
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// Defaults
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count_nxt = count;
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product_nxt = product;
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// update Negative and Zero flags
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// Use registered value of product so this adds an extra cycle
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// but this avoids having the 64-bit zero comparator on the
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// main adder path
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flags_nxt = { product[32], product[32:1] == 32'd0 };
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if ( count == 6'd0 )
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product_nxt = {33'd0, 1'd0, i_b_in, 1'd0 } ;
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else if ( count <= 6'd33 )
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product_nxt = { sum[33], sum, product[33:1]} ;
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else if ( count == 6'd34 && accumulate )
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begin
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// Note that bit 0 is not part of the product. It is used during the booth
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// multiplication algorithm
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product_nxt = { product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate
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end
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// Multiplication state counter
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if (count == 6'd0) // start
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count_nxt = enable ? 6'd1 : 6'd0;
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else if ((count == 6'd34 && !accumulate) || // MUL
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(count == 6'd35 && accumulate) ) // MLA
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count_nxt = 6'd0;
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else
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count_nxt = count + 1'd1;
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end
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always @ ( posedge i_clk )
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if ( !i_fetch_stall )
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begin
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count <= i_execute ? count_nxt : count;
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product <= i_execute ? product_nxt : product;
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o_done <= i_execute ? count == 6'd31 : o_done;
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end
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// Outputs
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assign o_out = product[32:1];
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assign o_flags = flags_nxt;
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initial begin
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o_done = 1'd0; // goes high 2 cycles before completion
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end
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endmodule
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