mirror of
https://github.com/MiSTer-devel/Archie_MiSTer.git
synced 2026-04-19 03:04:04 +00:00
e272019a2e
added more regs to reset for other modules added simulation some changes to be standard conform, mostly reordering of wire/reg defines
295 lines
10 KiB
VHDL
295 lines
10 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use ieee.math_real.all;
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use work.globals.all;
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entity etb is
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end entity;
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architecture arch of etb is
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signal clk : std_logic := '1';
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signal CLKCPU_I : std_logic := '1';
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signal CLKPIX_I : std_logic := '1';
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signal CEPIX_I : std_logic := '1';
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signal SELPIX_O : std_logic_vector(1 downto 0);
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signal CEAUD_I : std_logic;
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signal RESET_I : std_logic := '1';
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signal MEM_CYC_O : std_logic;
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signal MEM_STB_O : std_logic;
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signal MEM_WE_O : std_logic;
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signal MEM_ACK_I : std_logic;
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signal MEM_ERR_I : std_logic;
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signal MEM_RTY_I : std_logic;
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signal MEM_SEL_O : std_logic_vector(3 downto 0);
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signal MEM_CTI_O : std_logic_vector(2 downto 0);
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signal MEM_ADDR_O : std_logic_vector(21 downto 0);
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signal MEM_DAT_I : std_logic_vector(31 downto 0);
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signal MEM_DAT_O : std_logic_vector(31 downto 0);
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signal HSYNC : std_logic;
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signal VSYNC : std_logic;
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signal VIDEO_R : std_logic_vector(3 downto 0);
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signal VIDEO_G : std_logic_vector(3 downto 0);
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signal VIDEO_B : std_logic_vector(3 downto 0);
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signal VIDEO_EN : std_logic;
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signal VIDBASECLK_O : std_logic_vector(1 downto 0);
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signal VIDSYNCPOL_O : std_logic_vector(1 downto 0);
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signal I2C_DOUT : std_logic;
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signal I2C_DIN : std_logic;
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signal I2C_CLOCK : std_logic;
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signal DEBUG_LED : std_logic;
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signal img_mounted : std_logic_vector(1 downto 0);
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signal img_wp : std_logic;
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signal img_size : std_logic_vector(31 downto 0);
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signal sd_lba : std_logic_vector(31 downto 0) := (others => '0');
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signal sd_rd : std_logic_vector(1 downto 0);
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signal sd_wr : std_logic_vector(1 downto 0);
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signal sd_ack : std_logic;
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signal sd_buff_addr : std_logic_vector(7 downto 0) := (others => '0');
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signal sd_buff_dout : std_logic_vector(15 downto 0) := (others => '0');
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signal sd_buff_din : std_logic_vector(15 downto 0);
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signal sd_buff_wr : std_logic := '0';
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signal KBD_OUT_DATA : std_logic_vector(7 downto 0);
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signal KBD_OUT_STROBE : std_logic;
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signal KBD_IN_DATA : std_logic_vector(7 downto 0);
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signal KBD_IN_STROBE : std_logic;
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signal JOYSTICK0 : std_logic_vector(4 downto 0);
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signal JOYSTICK1 : std_logic_vector(4 downto 0);
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signal AUDIO_L : std_logic_vector(15 downto 0);
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signal AUDIO_R : std_logic_vector(15 downto 0);
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signal DDRAM_OUT_BUSY : std_logic := '0';
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signal DDRAM_OUT_DOUT : std_logic_vector(31 downto 0);
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signal DDRAM_OUT_DOUT_READY : std_logic;
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signal DDRAM_OUT_BURSTCNT : std_logic_vector(7 downto 0);
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signal DDRAM_OUT_ADDR : std_logic_vector(27 downto 0) := (others => '0');
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signal DDRAM_OUT_RD : std_logic;
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signal DDRAM_OUT_DIN : std_logic_vector(31 downto 0);
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signal DDRAM_OUT_BE : std_logic_vector(7 downto 0);
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signal DDRAM_OUT_WE : std_logic;
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type t_data is array(0 to (2**27)-1) of integer;
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type bit_vector_file is file of bit_vector;
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signal tx_command : std_logic_vector(31 downto 0);
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signal tx_bytes : integer range 0 to 4;
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signal tx_enable : std_logic := '0';
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begin
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clk <= not clk after 5 ns;
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CLKCPU_I <= not CLKCPU_I after 24 ns; -- not exactly 42Mhz
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CLKPIX_I <= not CLKPIX_I after 20 ns; -- ?
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CEPIX_I <= not CEPIX_I after 40 ns; -- ?
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process
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begin
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wait until rising_edge(clk);
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if (tx_enable = '1' and tx_command(7) = '1') then
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RESET_I <= tx_command(0);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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end if;
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end process;
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iarchimedes_top : entity work.archimedes_top
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generic map
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(
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CLKCPU => 42000000
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)
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port map
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(
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CLKCPU_I => CLKCPU_I ,
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CLKPIX_I => CLKPIX_I ,
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CEPIX_I => CEPIX_I ,
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SELPIX_O => SELPIX_O ,
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CEAUD_I => CEAUD_I ,
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RESET_I => RESET_I ,
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MEM_CYC_O => MEM_CYC_O ,
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MEM_STB_O => MEM_STB_O ,
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MEM_WE_O => MEM_WE_O ,
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MEM_ACK_I => MEM_ACK_I ,
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MEM_ERR_I => MEM_ERR_I ,
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MEM_RTY_I => MEM_RTY_I ,
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MEM_SEL_O => MEM_SEL_O ,
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MEM_CTI_O => MEM_CTI_O ,
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MEM_ADDR_O => MEM_ADDR_O ,
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MEM_DAT_I => MEM_DAT_I ,
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MEM_DAT_O => MEM_DAT_O ,
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HSYNC => HSYNC ,
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VSYNC => VSYNC ,
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VIDEO_R => VIDEO_R ,
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VIDEO_G => VIDEO_G ,
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VIDEO_B => VIDEO_B ,
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VIDEO_EN => VIDEO_EN ,
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VIDBASECLK_O => VIDBASECLK_O ,
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VIDSYNCPOL_O => VIDSYNCPOL_O ,
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I2C_DOUT => I2C_DOUT ,
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I2C_DIN => I2C_DIN ,
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I2C_CLOCK => I2C_CLOCK ,
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DEBUG_LED => DEBUG_LED ,
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img_mounted => img_mounted ,
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img_wp => img_wp ,
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img_size => img_size ,
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sd_lba => sd_lba ,
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sd_rd => sd_rd ,
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sd_wr => sd_wr ,
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sd_ack => sd_ack ,
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sd_buff_addr => sd_buff_addr ,
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sd_buff_dout => sd_buff_dout ,
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sd_buff_din => sd_buff_din ,
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sd_buff_wr => sd_buff_wr ,
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KBD_OUT_DATA => KBD_OUT_DATA ,
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KBD_OUT_STROBE => KBD_OUT_STROBE,
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KBD_IN_DATA => KBD_IN_DATA ,
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KBD_IN_STROBE => KBD_IN_STROBE ,
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JOYSTICK0 => JOYSTICK0 ,
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JOYSTICK1 => JOYSTICK1 ,
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AUDIO_L => AUDIO_L ,
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AUDIO_R => AUDIO_R
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);
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DDRAM_OUT_RD <= MEM_STB_O and not MEM_WE_O;
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DDRAM_OUT_WE <= MEM_STB_O and MEM_WE_O;
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DDRAM_OUT_DIN <= MEM_DAT_O;
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DDRAM_OUT_ADDR(23 downto 2) <= MEM_ADDR_O;
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--MEM_CYC_O
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--MEM_STB_O
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--MEM_WE_O
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--MEM_SEL_O
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--MEM_CTI_O
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--MEM_ADDR_O
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--MEM_DAT_O
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MEM_ACK_I <= DDRAM_OUT_DOUT_READY;
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MEM_ERR_I <= '0';
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MEM_RTY_I <= '0';
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MEM_DAT_I <= DDRAM_OUT_DOUT;
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iestringprocessor : entity work.estringprocessor
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port map
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(
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ready => '1',
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tx_command => tx_command,
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tx_bytes => tx_bytes,
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tx_enable => tx_enable,
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rx_command => x"00000000",
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rx_valid => '1'
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);
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process
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variable address : integer;
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variable data : t_data := (others => 0);
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variable readmodifywrite : std_logic_vector(31 downto 0);
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file infile : bit_vector_file;
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variable f_status : FILE_OPEN_STATUS;
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variable read_byte0 : std_logic_vector(7 downto 0);
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variable read_byte1 : std_logic_vector(7 downto 0);
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variable read_byte2 : std_logic_vector(7 downto 0);
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variable read_byte3 : std_logic_vector(7 downto 0);
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variable next_vector : bit_vector (3 downto 0);
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variable actual_len : natural;
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variable targetpos : integer;
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-- copy from std_logic_arith, not used here because numeric std is also included
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function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
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variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
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variable temp: integer;
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begin
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temp := ARG;
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for i in 0 to SIZE-1 loop
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if (temp mod 2) = 1 then
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result(i) := '1';
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else
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result(i) := '0';
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end if;
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if temp > 0 then
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temp := temp / 2;
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elsif (temp > integer'low) then
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temp := (temp - 1) / 2; -- simulate ASR
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else
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temp := temp / 2; -- simulate ASR
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end if;
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end loop;
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return result;
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end;
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begin
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DDRAM_OUT_DOUT_READY <= '0';
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while (0 = 0) loop
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-- data from file
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COMMAND_FILE_ACK <= '0';
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if COMMAND_FILE_START = '1' then
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assert false report "received" severity note;
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assert false report COMMAND_FILE_NAME(1 to COMMAND_FILE_NAMELEN) severity note;
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file_open(f_status, infile, COMMAND_FILE_NAME(1 to COMMAND_FILE_NAMELEN), read_mode);
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targetpos := COMMAND_FILE_TARGET / 4;
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while (not endfile(infile)) loop
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read(infile, next_vector, actual_len);
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read_byte0 := CONV_STD_LOGIC_VECTOR(bit'pos(next_vector(0)), 8);
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read_byte1 := CONV_STD_LOGIC_VECTOR(bit'pos(next_vector(1)), 8);
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read_byte2 := CONV_STD_LOGIC_VECTOR(bit'pos(next_vector(2)), 8);
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read_byte3 := CONV_STD_LOGIC_VECTOR(bit'pos(next_vector(3)), 8);
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if (COMMAND_FILE_ENDIAN = '1') then
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data(targetpos) := to_integer(signed(read_byte3 & read_byte2 & read_byte1 & read_byte0));
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else
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data(targetpos) := to_integer(signed(read_byte0 & read_byte1 & read_byte2 & read_byte3));
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end if;
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targetpos := targetpos + 1;
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end loop;
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file_close(infile);
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COMMAND_FILE_ACK <= '1';
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end if;
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if (DDRAM_OUT_BUSY = '0') then
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address := to_integer(unsigned(DDRAM_OUT_ADDR)) / 4;
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while (DDRAM_OUT_RD = '1') loop
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DDRAM_OUT_DOUT_READY <= '1';
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DDRAM_OUT_DOUT <= std_logic_vector(to_signed(data(address), 32));
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wait until rising_edge(CLKCPU_I);
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wait for 1 ns;
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address := address + 1;
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end loop;
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DDRAM_OUT_DOUT_READY <= '0';
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if (DDRAM_OUT_WE = '1') then
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data(address) := to_integer(unsigned(DDRAM_OUT_DIN));
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end if;
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end if;
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wait until rising_edge(CLKCPU_I);
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end loop;
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end process;
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end architecture;
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