mirror of
https://github.com/MiSTer-devel/Archie_MiSTer.git
synced 2026-04-19 03:04:04 +00:00
e272019a2e
added more regs to reset for other modules added simulation some changes to be standard conform, mostly reordering of wire/reg defines
51 lines
1.1 KiB
Batchfile
51 lines
1.1 KiB
Batchfile
RMDIR /s /q work
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MKDIR work
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vmap altera_mf altera_mf
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vlib work
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vlog -O0 +incdir+./../rtl/ ../rtl/archimedes_top.v ^
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../rtl/memc.v ^
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../rtl/memc_translator.v ^
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../rtl/vidc.v ^
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../rtl/vidc_audio.v ^
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../rtl/vidc_dmachannel.v ^
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../rtl/vidc_fifo.v ^
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../rtl/vidc_timing.v ^
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../rtl/ioc.v ^
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../rtl/ioc_irq.v ^
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../rtl/fdc1772.v ^
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../rtl/floppy.v ^
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../rtl/latches.v ^
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../rtl/sram_line_en.v ^
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../rtl/sram_byte_en.v ^
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../rtl/podules.v
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vlog -O0 +incdir+./../rtl/amber/ ../rtl/amber/a23_alu.v ^
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../rtl/amber/a23_barrel_shift.v ^
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../rtl/amber/a23_barrel_shift_fpga.v ^
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../rtl/amber/a23_cache.v ^
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../rtl/amber/a23_config_defines.v ^
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../rtl/amber/a23_coprocessor.v ^
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../rtl/amber/a23_core.v ^
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../rtl/amber/a23_decode.v ^
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../rtl/amber/a23_execute.v ^
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../rtl/amber/a23_fetch.v ^
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../rtl/amber/a23_multiply.v ^
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../rtl/amber/a23_ram_register_bank.v ^
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../rtl/amber/a23_register_bank.v ^
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../rtl/amber/a23_wishbone.v
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vcom -O5 -2008 -vopt -quiet -work work ^
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../rtl/bram.vhd
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vcom -O5 -2008 -vopt -quiet -work work ^
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cpu_export.vhd
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vcom -O5 -vopt -quiet -work work ^
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globals.vhd ^
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stringprocessor.vhd ^
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tb.vhd
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