mirror of
https://github.com/MiSTer-devel/Archie_MiSTer.git
synced 2026-04-19 03:04:04 +00:00
e272019a2e
added more regs to reset for other modules added simulation some changes to be standard conform, mostly reordering of wire/reg defines
17 lines
561 B
Plaintext
17 lines
561 B
Plaintext
Tested with Modelsim 10.5
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- compile with vcom_all.bat. Make sure you have altera_mf library in folder, generated from quartus
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- run modelsim with vsim_start.bat
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- run all
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Simulation will now wait for input from outside
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Run Luascript run.lua with "lua run.lua" from folder lua_tests
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It will upload riscos into the testbench memory and let the cpu run it
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Current test checks for reset working.
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CPU Export will write a log with every register change for every clock cycle.
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This can be used to compare(with a diff tool) original behavior to any changes made.
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