mirror of
https://github.com/MiSTer-devel/Archie_MiSTer.git
synced 2026-04-19 03:04:04 +00:00
e272019a2e
added more regs to reset for other modules added simulation some changes to be standard conform, mostly reordering of wire/reg defines
13 lines
349 B
VHDL
13 lines
349 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package globals is
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signal COMMAND_FILE_ENDIAN : std_logic;
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signal COMMAND_FILE_NAME : string(1 to 1024);
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signal COMMAND_FILE_NAMELEN : integer;
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signal COMMAND_FILE_TARGET : integer;
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signal COMMAND_FILE_START : std_logic;
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signal COMMAND_FILE_ACK : std_logic;
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end package globals; |