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88 lines
2.3 KiB
Systemverilog
88 lines
2.3 KiB
Systemverilog
//
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// ide.sv
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//
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// Copyright (c) 2019 György Szombathelyi
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// altera message_off 10030
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module podule_ide (
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input clk, // system clock.
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input reset,
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input cpu_sel,
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input cpu_we,
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input [13:2] cpu_adr,
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input [15:0] cpu_dat_i,
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output [15:0] cpu_dat_o,
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output hdd_led,
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// place any signals that need to be passed up to the top after here.
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output [5:0] ide_req,
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input [4:0] ide_address,
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input ide_write,
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input [15:0] ide_writedata,
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input ide_read,
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output [15:0] ide_readdata
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);
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// RISC Developments IDE Interface in Podule 0
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reg [7:0] rd_rom[16384];
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initial $readmemh("rtl/riscdevide_rom.hex", rd_rom);
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wire reg_sel = cpu_sel && cpu_adr[13:10] == 4'hA;
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wire page_sel = cpu_sel && cpu_adr[13:02] == 12'h800 && cpu_we ;
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reg [2:0] rd_page;
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always @(posedge clk) begin
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if (reset) rd_page <= 0;
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else if (page_sel) rd_page <= cpu_dat_i[2:0];
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end
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reg [7:0] rd_rom_q;
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always @(posedge clk) rd_rom_q <= rd_rom[{rd_page, cpu_adr[12:2]}];
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wire [2:0] ide_reg = cpu_adr[4:2];
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wire [15:0] data_out;
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assign cpu_dat_o = ~reg_sel ? {8'd0, rd_rom_q} : ((!ide_reg) ? data_out : { data_out[7:0], data_out[7:0] });
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assign ide_req[5:3] = 0;
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ide ide
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(
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.clk(clk),
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.rst_n(~reset),
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.drq(hdd_led),
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.use_fast(0),
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.io_32(0),
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.io_address(ide_reg),
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.io_read(~cpu_we & reg_sel),
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.io_readdata(data_out),
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.io_write(cpu_we & reg_sel),
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.io_writedata(cpu_dat_i),
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.request(ide_req[2:0]),
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.mgmt_address(ide_address[3:0]),
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.mgmt_write(~ide_address[4] & ide_write),
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.mgmt_writedata(ide_writedata),
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.mgmt_read(~ide_address[4] & ide_read),
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.mgmt_readdata(ide_readdata)
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);
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endmodule
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