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https://github.com/MiSTer-devel/Archie_MiSTer.git
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263 lines
7.2 KiB
Verilog
263 lines
7.2 KiB
Verilog
`timescale 1ns / 1ps
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/* ioc.v
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Copyright (c) 2012-2015, Stephen J. Leary
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the <organization> nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module ioc
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(
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input clkcpu, // cpu bus clock domain
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output reg clk2m_en,
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output reg clk7m_en,
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input por, // power on reset signal.
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input [5:0] c_in,
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output[5:0] c_out,
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output [7:1] select, // perhiperhal select lines
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output sext, // external perhiperhal select
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input [1:0] fh, // fast high interrupt.
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input [7:0] il, // active low interrupt lines
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input ir, //
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// "wishbone" bus
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input wb_we,
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input wb_stb,
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input wb_cyc,
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input [6:2] wb_adr,
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input [7:0] wb_dat_i,
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output [7:0] wb_dat_o,
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// perhaps rename but its part of an IOC bus cycle.
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input [2:0] wb_bank,
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// interrupts
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output irq,
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output firq,
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// keyboard interface to arm controller. Data is valid
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// in rising edge of strobe
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output reg [7:0] kbd_out_data,
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output reg kbd_out_strobe,
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input [7:0] kbd_in_data,
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input kbd_in_strobe
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);
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reg [4:0] clk2en_counter = 0;
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reg [2:0] clk7en_counter = 0;
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wire [7:0] irqa_dout, irqb_dout, firq_dout;
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wire irqa_req, irqb_req, firq_req;
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wire irqa_selected, irqb_selected, firq_selected;
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wire ctrl_selected = wb_adr[6:2] == 5'd0 /* synthesis keep */;
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wire [7:0] ctrl_dout;
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reg [5:0] ctrl_state;
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wire serial_selected = wb_adr[6:2] == 5'd1 /* synthesis keep */;
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wire write_request = (wb_bank == 3'b000) & wb_stb & wb_cyc & wb_we;
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wire read_request = (wb_bank == 3'b000) & wb_stb & wb_cyc & !wb_we;
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// keyboard input is valid on rising edge of kbd_in_strobe. Latch data then
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// and set irq
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reg [7:0] kbd_in_data_latch;
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reg kbd_in_irq_ack;
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reg kbd_in_irq;
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// input data irq is cleared when cpu reads input port
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always @(posedge clkcpu or posedge kbd_in_irq_ack) begin
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if (kbd_in_irq_ack) kbd_in_irq <= 0;
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else if (kbd_in_strobe) begin
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kbd_in_data_latch <= kbd_in_data;
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kbd_in_irq <= 1;
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end
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end
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// faked kbd tx timing
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reg[4:0] txcount = 5'd0;
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wire txdone = txcount == 5'd0 /* synthesis keep */;
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// edge detect for IR
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reg ir_r;
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wire ir_edge;
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// Instantiate the Unit Under Test (UUT)
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ioc_irq #(.ADDRESS(2'b01), .PERMBITS(8'h80), .CANCLEAR(8'b01111111)) IRQA
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(
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.clkcpu ( clkcpu ),
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.reset ( por ),
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.i ( {timer[2].reload, timer[1].reload, timer[0].reload, por, ir_edge, 3'b000}),
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.irq ( irqa_req ),
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.c ( 8'h00 ),
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.addr ( wb_adr[6:2] ),
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.din ( wb_dat_i ),
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.dout ( irqa_dout ),
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.sel ( irqa_selected ),
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.write ( write_request )
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);
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// Instantiate the Unit Under Test (UUT)
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ioc_irq #(.ADDRESS(2'b10), .CANCLEAR(8'b00000000)) IRQB
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(
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.clkcpu ( clkcpu ),
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.reset ( por ),
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.i ( { kbd_in_irq, txdone, ~il[5:0]}),
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.c ( {!kbd_in_irq, ~txdone, il[5:0]}),
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.irq ( irqb_req ),
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.addr ( wb_adr[6:2] ),
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.din ( wb_dat_i ),
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.dout ( irqb_dout ),
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.sel ( irqb_selected ),
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.write ( write_request )
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);
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ioc_irq #(.ADDRESS(2'b11), .CANCLEAR(8'd0)) FIRQ
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(
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.clkcpu ( clkcpu ),
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.reset ( por ),
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.i ( {6'h00, fh[1:0]} ),
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.c ( {6'h00, ~fh[1:0]}),
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.irq ( firq_req ),
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.addr ( wb_adr[6:2] ),
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.din ( wb_dat_i ),
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.dout ( firq_dout ),
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.sel ( firq_selected ),
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.write ( write_request )
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);
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generate
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genvar c;
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for (c = 0; c < 4; c = c + 1) begin: timer
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reg [15:0] latch_i;
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reg [15:0] counter;
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reg [15:0] latch_o;
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reg reload;
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wire selected = wb_adr[6] & (c[1:0] == wb_adr[5:4]);
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wire [7:0] out = wb_adr[2] ? latch_o[15:8] : latch_o[7:0];
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initial begin
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latch_i = 16'd0;
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counter = 16'd0;
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latch_o = 16'd0;
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reload = 1'b0;
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end
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always @(posedge clkcpu) begin
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reload <= 1'b0;
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if (write_request & selected) begin
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case (wb_adr[3:2])
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2'b00: latch_i[7:0] <= wb_dat_i;
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2'b01: latch_i[15:8] <= wb_dat_i;
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2'b10: counter <= {latch_i[15:4],4'd0};
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2'b11: latch_o <= counter;
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endcase
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end else if (clk2m_en) begin
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counter <= counter - 15'd1;
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if (~|counter) begin
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reload <= 1'b1;
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counter <= {latch_i[15:4],4'd0};
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end
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end
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end
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end
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endgenerate
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// here we generate the ack signal and the 2mhz enable.
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always @(posedge clkcpu) begin
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if (por) begin
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ctrl_state <= 6'h3F;
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ir_r <= 1'b1;
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clk2en_counter <= 0;
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clk7en_counter <= 0;
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clk2m_en <= 0;
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clk7m_en <= 0;
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end else begin
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// generate strobe one clock cycle after data has been latched
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kbd_out_strobe <= !txdone;
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kbd_in_irq_ack <= serial_selected && read_request;
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ir_r <= ir;
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if (!txdone && timer[3].reload) begin
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txcount <= txcount - 4'd1;
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end
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// increment the clock counter. 42 MHz clkcpu assumed.
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clk2en_counter <= clk2en_counter + 1'd1;
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if (clk2en_counter == 20) clk2en_counter <= 0;
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clk2m_en <= !clk2en_counter;
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clk7en_counter <= clk7en_counter + 1'd1;
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if (clk7en_counter == 5) clk7en_counter <= 0;
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clk7m_en <= !clk7en_counter;
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if (write_request & ctrl_selected) begin
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ctrl_state <= wb_dat_i[5:0];
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end
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if (write_request & serial_selected) begin
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// simulate a serial port write to the console.
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kbd_out_strobe <= 1'b0;
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kbd_out_data <= wb_dat_i[7:0];
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txcount <= 5'd20;
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end
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end
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end
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// external perhiperhal stuff.
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assign {select, sext} = wb_bank ? ((8'd1 << wb_bank) | 8'd1) : 8'd0;
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assign c_out = ctrl_state;
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assign ctrl_dout = { ir, 1'b1, c_in & c_out };
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assign ir_edge = ~ir_r & ir;
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assign wb_dat_o =
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~read_request ? 8'hFF :
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ctrl_selected ? ctrl_dout :
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serial_selected ? kbd_in_data_latch :
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irqa_selected ? irqa_dout :
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irqb_selected ? irqb_dout :
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firq_selected ? firq_dout :
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timer[0].selected ? timer[0].out :
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timer[1].selected ? timer[1].out :
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timer[2].selected ? timer[2].out :
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timer[3].selected ? timer[3].out : 8'hFF;
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assign irq = irqa_req | irqb_req;
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assign firq = firq_req;
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// sext is high if any bits of select are high
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endmodule
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