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122 lines
3.1 KiB
Verilog
122 lines
3.1 KiB
Verilog
//
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// hps_ext for Archie
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//
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// Copyright (c) 2020 Alexey Melnikov
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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///////////////////////////////////////////////////////////////////////
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module hps_ext
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(
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input clk_sys,
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inout [35:0] EXT_BUS,
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input [7:0] kbd_out_data,
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input kbd_out_strobe,
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output reg [7:0] kbd_in_data,
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output reg kbd_in_strobe,
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input [7:0] cmos_cnt,
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input [15:0] ide_din,
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output reg [15:0] ide_dout,
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output reg [4:0] ide_addr,
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output reg ide_rd,
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output reg ide_wr,
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input [5:0] ide_req
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);
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assign EXT_BUS[15:0] = io_dout;
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wire [15:0] io_din = EXT_BUS[31:16];
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assign EXT_BUS[32] = io_dout_en;
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wire io_strobe = EXT_BUS[33];
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wire io_enable = EXT_BUS[34] | fp_enable;
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wire fp_enable = EXT_BUS[35];
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localparam EXT_CMD_MIN = 4;
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localparam EXT_CMD_MAX = 5;
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localparam EXT_CMD_MIN2= 'h61;
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localparam EXT_CMD_MAX2= 'h63;
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reg [15:0] io_dout;
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reg io_dout_en;
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always@(posedge clk_sys) begin
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reg [7:0] cmd;
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reg ide_cs = 0;
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reg [3:0] byte_cnt;
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reg old_out_strobe = 0;
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reg kbd_out_data_available = 0;
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{ide_rd, ide_wr} <= 0;
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if((ide_rd | ide_wr) & ~&ide_addr[3:0]) ide_addr <= ide_addr + 1'd1;
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kbd_in_strobe <= 0;
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old_out_strobe <= kbd_out_strobe;
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if(~old_out_strobe && kbd_out_strobe) kbd_out_data_available <= 1;
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if(~io_enable) begin
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byte_cnt <= 0;
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ide_cs <= 0;
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io_dout <= 0;
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io_dout_en <= 0;
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end else begin
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if(io_strobe) begin
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io_dout <= 0;
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if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
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ide_dout <= io_din;
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if(byte_cnt == 1) begin
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ide_addr <= {io_din[8],io_din[3:0]};
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ide_cs <= (io_din[15:9] == 7'b1111000);
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end
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if(byte_cnt == 0) begin
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cmd <= io_din[7:0];
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io_dout_en <= fp_enable ? !io_din : ((io_din >= EXT_CMD_MIN && io_din <= EXT_CMD_MAX) || (io_din >= EXT_CMD_MIN2 && io_din <= EXT_CMD_MAX2));
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if(io_din == 'h63) io_dout <= {4'hE, 2'b00, 2'b00, 2'b00, ide_req};
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if(io_din == 'h00) io_dout <= cmos_cnt;
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end
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else begin
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case(cmd)
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'h04: if(byte_cnt == 1) begin
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io_dout[7:0] <= { 4'ha, 3'b000, kbd_out_data_available };
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kbd_out_data_available <= 0;
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end
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else begin
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io_dout[7:0] <= kbd_out_data;
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end
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'h05: begin
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if(byte_cnt == 1) kbd_in_strobe <= 1;
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kbd_in_data <= io_din[7:0];
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end
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'h61: if(byte_cnt >= 3 && ide_cs) begin
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ide_wr <= 1;
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end
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'h62: if(byte_cnt >= 3 && ide_cs) begin
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io_dout <= ide_din;
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ide_rd <= 1;
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end
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default: ;
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endcase
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end
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end
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end
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end
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endmodule
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