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82 lines
3.7 KiB
Verilog
82 lines
3.7 KiB
Verilog
//////////////////////////////////////////////////////////////////
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// //
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// Memory configuration and Wishbone address decoding //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// This module provides a set of functions that are used to //
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// decode memory addresses so other modules know if an address //
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// is for example in main memory, or boot memory, or a UART //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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// e.g. 24 for 32MBytes, 26 for 128MBytes
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localparam MAIN_MSB = 26;
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// e.g. 13 for 4k words
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localparam BOOT_MSB = 13;
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localparam MAIN_BASE = 32'h0000_0000; /* Main Memory */
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localparam PHYS_BASE = 32'h0200_0000; /* Physical Memory */
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localparam IO_BASE = 32'h0300_0000; /* Physical Memory */
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localparam ROM_BASE = 32'h0340_0000; /* Uncachable Boot Memory */
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localparam ROM_TOP = 32'h0400_0000; /* Uncachable Boot Memory */
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function in_rom_mem;
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input [31:0] address;
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begin
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in_rom_mem = (address >= ROM_BASE &&
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address < (ROM_TOP));
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end
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endfunction
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function in_main_mem;
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input [31:0] address;
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begin
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in_main_mem = (address >= MAIN_BASE &&
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address < (IO_BASE));
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end
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endfunction
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// Used in fetch.v and l2cache.v to allow accesses to these addresses
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// to be cached
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function in_cachable_mem;
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input [31:0] address;
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begin
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in_cachable_mem = 0;
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end
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endfunction
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