diff --git a/Archie.sv b/Archie.sv
index 6bd435f..35621fc 100644
--- a/Archie.sv
+++ b/Archie.sv
@@ -221,15 +221,15 @@ end
 
 
 wire pll_ready;
-wire clk_128m;
-wire clk_32m;
+wire clk_mem;
+wire clk_sys;
 
 pll pll
 (
 	.refclk(CLK_50M),
-	.outclk_0(clk_128m),
+	.outclk_0(clk_mem),
 	.outclk_1(SDRAM_CLK),
-	.outclk_2(clk_32m),
+	.outclk_2(clk_sys),
 	.locked(pll_ready)
 );
 
@@ -271,7 +271,7 @@ wire        img_readonly;
 
 hps_io #(.STRLEN($size(CONF_STR)>>3), .WIDE(1), .VDNUM(2)) hps_io
 (
-	.clk_sys(clk_32m),
+	.clk_sys(clk_sys),
 	.HPS_BUS(HPS_BUS),
 
 	.conf_str(CONF_STR),
@@ -296,17 +296,17 @@ hps_io #(.STRLEN($size(CONF_STR)>>3), .WIDE(1), .VDNUM(2)) hps_io
 	.ioctl_wr(ioctl_wr),
 	.ioctl_wait(loader_stb),
 
-	.sd_lba(sd_lba),
-	.sd_rd(sd_rd),
-	.sd_wr(sd_wr),
-	.sd_ack(sd_ack),
-	.sd_buff_addr(sd_buff_addr),
-	.sd_buff_dout(sd_buff_dout),
-	.sd_buff_din(sd_buff_din),
-	.sd_buff_wr(sd_buff_wr),
-	.img_mounted(img_mounted),
-	.img_size(img_size),
-	.img_readonly(img_readonly)
+	.sd_lba(sd_lba),
+	.sd_rd(sd_rd),
+	.sd_wr(sd_wr),
+	.sd_ack(sd_ack),
+	.sd_buff_addr(sd_buff_addr),
+	.sd_buff_dout(sd_buff_dout),
+	.sd_buff_din(sd_buff_din),
+	.sd_buff_wr(sd_buff_wr),
+	.img_mounted(img_mounted),
+	.img_size(img_size),
+	.img_readonly(img_readonly)
 );
 
 assign AUDIO_S = 0;
@@ -339,7 +339,7 @@ wire 			i2c_din, i2c_dout, i2c_clock;
 
 archimedes_top ARCHIMEDES
 (
-	.CLKCPU_I	( clk_32m			),
+	.CLKCPU_I	( clk_sys			),
 	.CLKPIX_I	( CLK_VIDEO			),
 	.CEPIX_O	 	( CE_PIXEL			),
 
@@ -372,17 +372,17 @@ archimedes_top ARCHIMEDES
 
 	.DEBUG_LED	(    					),
 
-	.sd_lba       ( sd_lba       ),
-	.sd_rd        ( sd_rd        ),
-	.sd_wr        ( sd_wr        ),
-	.sd_ack       ( sd_ack       ),
-	.sd_buff_addr ( sd_buff_addr ),
-	.sd_buff_dout ( sd_buff_dout ),
-	.sd_buff_din  ( sd_buff_din  ),
-	.sd_buff_wr   ( sd_buff_wr   ),
-	.img_mounted  ( img_mounted  ),
-	.img_size     ( img_size     ),
-	.img_wp       ( img_readonly ),
+	.sd_lba       ( sd_lba       ),
+	.sd_rd        ( sd_rd        ),
+	.sd_wr        ( sd_wr        ),
+	.sd_ack       ( sd_ack       ),
+	.sd_buff_addr ( sd_buff_addr ),
+	.sd_buff_dout ( sd_buff_dout ),
+	.sd_buff_din  ( sd_buff_din  ),
+	.sd_buff_wr   ( sd_buff_wr   ),
+	.img_mounted  ( img_mounted  ),
+	.img_size     ( img_size     ),
+	.img_wp       ( img_readonly ),
 
 	.KBD_OUT_DATA   ( kbd_out_data   ),
 	.KBD_OUT_STROBE ( kbd_out_strobe ),
@@ -406,7 +406,7 @@ wire			ram_ready;
 sdram SDRAM
 (
 	// wishbone interface
-	.wb_clk		(clk_32m		 ),
+	.wb_clk		(clk_sys		 ),
 	.wb_stb		(ram_stb		 ),
 	.wb_cyc		(ram_cyc		 ),
 	.wb_we		(ram_we		 ),
@@ -419,7 +419,7 @@ sdram SDRAM
 	.wb_cti		(core_cti_o	 ),
 
 	// SDRAM Interface
-	.sd_clk		(clk_128m	 ),
+	.sd_clk		(clk_mem	 ),
 	.sd_rst		(~pll_ready	 ),
 
 	.sd_cke		(SDRAM_CKE	 ),
@@ -436,7 +436,7 @@ sdram SDRAM
 
 i2cSlave CMOS
 (
-	.clk		(clk_32m	 ),
+	.clk		(clk_sys	 ),
 	.rst		(~pll_ready ),
 	.sdaIn	(i2c_din	 ),
 	.sdaOut	(i2c_dout	 ),
@@ -457,7 +457,7 @@ wire [7:0] cmos_dl_addr;
 wire [1:0] cmos_dl_wr;
 
 reg loader_stb = 0;
-always @(posedge clk_32m) begin 
+always @(posedge clk_sys) begin 
 	if (ram_ack) loader_stb <= 0;
 	if(riscos_dl & ioctl_wr) loader_stb <= 1;
 
diff --git a/fdc1772.v b/fdc1772.v
index 03f13e9..3a653c4 100644
--- a/fdc1772.v
+++ b/fdc1772.v
@@ -61,7 +61,7 @@ module fdc1772 (
 		input            sd_buff_wr
 );
 
-localparam CLK = 32000000;
+localparam CLK = 42000000;
 localparam CLK_EN = 8000000;
 
 // -------------------------------------------------------------------------
diff --git a/ioc.v b/ioc.v
index d80bfb2..33d01c0 100644
--- a/ioc.v
+++ b/ioc.v
@@ -69,8 +69,7 @@ module ioc(
 		input            kbd_in_strobe
 );
 
-reg [3:0] 	clk2m_count;
-reg [1:0] 	clk8m_count;
+reg [4:0]   clken_counter;
 
 wire [7:0]	irqa_dout, irqb_dout, firq_dout;
 wire			irqa_req, irqb_req, firq_req;
@@ -85,23 +84,17 @@ wire		serial_selected = wb_adr[6:2] == 5'd1 /* synthesis keep */;
 wire write_request 	= (wb_bank == 3'b000) & wb_stb & wb_cyc & wb_we;
 wire read_request 	= (wb_bank == 3'b000) & wb_stb & wb_cyc & !wb_we;
 
-// input data irq is cleared when cpu reads input port
-reg kbd_in_irq_ack;
-reg kbd_in_irq = 0;
-
-// keyboard input is valid on kbd_in_strobe. Latch data then
+// keyboard input is valid on rising edge of kbd_in_strobe. Latch data then
 // and set irq
 reg [7:0] kbd_in_data_latch;
-
-always @(posedge clkcpu) begin
-	reg old_ack;
-	
-	old_ack <= kbd_in_irq_ack;
-	if(kbd_in_strobe) begin
+reg kbd_in_irq_ack;
+reg kbd_in_irq;
+// input data irq is cleared when cpu reads input port
+always @(posedge clkcpu or posedge kbd_in_irq_ack) begin
+	if (kbd_in_irq_ack) kbd_in_irq <= 0;
+	else if (kbd_in_strobe) begin
 		kbd_in_data_latch <= kbd_in_data;
 		kbd_in_irq <= 1;
-	end else if(~old_ack & kbd_in_irq_ack) begin
-		kbd_in_irq <= 0;
 	end
 end
 
@@ -235,9 +228,6 @@ initial begin
 
 	ctrl_state = 6'h3F;
 
-	clk8m_count = 'd0;
-	clk2m_count = 'd0;
-
 	ir_r = 1'b1;
 	
 end
@@ -259,10 +249,10 @@ always @(posedge clkcpu) begin
 		
 	end
 
-	// increment the clock counters.
-	clk2m_count <= clk2m_count + 1'd1;
-	clk8m_count <= clk8m_count + 1'd1;
-	
+	// increment the clock counter. 42 MHz clkcpu assumed.
+	clken_counter <= clken_counter + 1'd1;
+	if (clken_counter == 20) clken_counter <= 0;
+
 	if (write_request & ctrl_selected) begin 
 	
 		ctrl_state <= wb_dat_i[5:0];
@@ -294,9 +284,8 @@ assign ctrl_dout = { ir, 1'b1, c_in & c_out };
 
 assign ir_edge = ~ir_r & ir;
 
-// pulse the 2mhz & 8mhz clock enable line high when all the bits are set. 
-assign clk2m_en = &clk2m_count;
-assign clk8m_en = &clk8m_count;
+assign clk2m_en = !clken_counter;
+assign clk8m_en = clken_counter == 0 || clken_counter == 5 || clken_counter == 10 || clken_counter == 15;
 
 assign wb_dat_o = 	read_request ?
 					(ctrl_selected ?  ctrl_dout :
diff --git a/sdram.v b/sdram.v
index 83c5175..dbe39aa 100644
--- a/sdram.v
+++ b/sdram.v
@@ -31,10 +31,10 @@ module sdram
 	input            sd_clk,		// sdram is accessed at 128MHz
 	input            sd_rst,		// reset the sdram controller.
 	output           sd_cke,		// clock enable.
-	inout  reg[15:0] sd_dq,		// 16 bit bidirectional data bus
-	output reg[12:0] sd_addr,	// 13 bit multiplexed address bus
-	output reg [1:0] sd_dqm = 2'b00,		// two byte masks
-	output reg [1:0] sd_ba = 2'b00,		// two banks
+	inout  reg[15:0]sd_dq,		// 16 bit bidirectional data bus
+	output reg[12:0]sd_addr,	// 13 bit multiplexed address bus
+	output reg[1:0]	sd_dqm = 2'b00,		// two byte masks
+	output reg[1:0]	sd_ba = 2'b00,		// two banks
 	output           sd_cs_n,	// a single chip select
 	output           sd_we_n,	// write enable
 	output           sd_ras_n,	// row address select
@@ -45,7 +45,7 @@ module sdram
 
 	input            wb_clk,     // 32MHz chipset clock to which sdram state machine is synchonized	
 	input     [31:0] wb_dat_i,	// data input from chipset/cpu
-	output reg[31:0] wb_dat_o = 0,	// data output to chipset/cpu
+	output reg[31:0]wb_dat_o = 0,	// data output to chipset/cpu
 	output reg       wb_ack = 0, 
 	input     [23:0] wb_adr,		// lower 2 bits are ignored.
 	input      [3:0] wb_sel,		// 
@@ -81,15 +81,24 @@ reg [3:0] t;
 reg [4:0] reset;
 reg[31:0] sd_dat	  = 0; // data output to chipset/cpu
 reg[31:0] sd_dat_nxt = 0; // data output to chipset/cpu
-reg		 sd_stb 	= 0;   // copy of the wishbone bus signal.
-reg		 sd_we 	= 0;   // copy of the wishbone bus signal.
-reg		 sd_cyc 	= 0;   // copy of the wishbone bus signal.
-reg		 sd_burst = 0;
-reg [3:0] sd_cycle = 0;
-reg		 sd_done  = 0;
-reg [3:0] sd_cmd 	= 0;   // current command sent to sd ram
-reg [9:0] sd_refresh = 0;
-reg		 sd_auto_refresh = 0; 
+
+reg			sd_stb 	= 1'b0; // copy of the wishbone bus signal.
+reg			sd_we 	= 1'b0; // copy of the wishbone bus signal.
+reg			sd_cyc 	= 1'b0; // copy of the wishbone bus signal.
+reg			sd_burst = 1'b0;
+
+reg	[3:0]	sd_cycle= 4'd0;
+reg			sd_done = 1'b0;
+
+reg [3:0] 	sd_cmd 	= 4'd0;   // current command sent to sd ram
+
+reg [9:0]	sd_refresh = 10'd0;
+reg			sd_auto_refresh = 1'b0; 
+wire		sd_req = wb_stb & wb_cyc & ~wb_ack;
+reg  [11:0] sd_active_row[3:0];
+reg   [3:0] sd_bank_active;
+wire  [1:0] sd_bank = wb_adr[22:21];
+wire [11:0] sd_row = wb_adr[20:9];
 
 initial begin 
 	t			= 4'd0;
@@ -98,9 +107,10 @@ initial begin
 	sd_cmd 	= CMD_INHIBIT;
 end
 
-localparam CYCLE_RAS_START  = 4'd1;  
+localparam CYCLE_PRECHARGE  = 4'd0;
+localparam CYCLE_RAS_START  = 4'd3;
 localparam CYCLE_RFSH_START = CYCLE_RAS_START; 
-localparam CYCLE_CAS0       = CYCLE_RFSH_START  + RASCAS_DELAY; 
+localparam CYCLE_CAS0 		= CYCLE_RAS_START  + RASCAS_DELAY;
 localparam CYCLE_CAS1       = CYCLE_CAS0 + 4'd1;		
 localparam CYCLE_CAS2       = CYCLE_CAS1 + 4'd1;		
 localparam CYCLE_CAS3       = CYCLE_CAS2 + 4'd1;				
@@ -108,22 +118,30 @@ localparam CYCLE_READ0      = CYCLE_CAS0 + CAS_LATENCY + 4'd1;
 localparam CYCLE_READ1      = CYCLE_READ0+ 1'd1;
 localparam CYCLE_READ2      = CYCLE_READ1+ 1'd1;
 localparam CYCLE_READ3      = CYCLE_READ2+ 1'd1;
-localparam CYCLE_END        = 4'hF;
-localparam CYCLE_WR_END     = CYCLE_CAS1 + 4'd4;
+localparam CYCLE_END	   	= CYCLE_READ3+ 1'd1;
 localparam CYCLE_RFSH_END   = CYCLE_RFSH_START + RFC_DELAY; 
 
 localparam RAM_CLK          = 128000000;
 localparam REFRESH_PERIOD   = (RAM_CLK / (16 * 8192)) - CYCLE_END;
+
+`ifdef VERILATOR
+reg [15:0] sd_q;
+assign sd_dq = (sd_writing && (sd_cycle == CYCLE_CAS1 || sd_cycle == CYCLE_CAS2)) ? sd_q : 16'bZZZZZZZZZZZZZZZZ;
+`endif
  
 always @(posedge sd_clk) begin 
 
+`ifndef VERILATOR
+		sd_dq <= 16'bZZZZZZZZZZZZZZZZ;
+`endif
+	sd_cmd <= CMD_NOP;
+
 	if (sd_rst) begin 
 		t			<= 4'd0;
 		reset 	<= 5'h1f;
 		sd_addr	<= 13'd0;
 		sd_ready  <= 0;
 	end else begin
-		sd_dq <= 16'bZZZZZZZZZZZZZZZZ;
 		if (!sd_ready) begin
 			t <= t + 4'd1;
 
@@ -157,8 +175,7 @@ always @(posedge sd_clk) begin
 			// bring the wishbone bus signal into the ram clock domain.
 
 			sd_we	<= wb_we;
-			sd_cmd	<= CMD_INHIBIT;
-			if (wb_stb & wb_cyc & ~wb_ack) begin 
+			if (sd_req) begin 
 				sd_stb	<= wb_stb;
 				sd_cyc	<= wb_cyc;
 			end
@@ -172,6 +189,9 @@ always @(posedge sd_clk) begin
 			if ((sd_refresh > REFRESH_PERIOD) && (sd_cycle == 4'd0)) begin 
 				sd_auto_refresh <= 1'b1;
 				sd_refresh		<= 10'd0;
+				sd_cmd			<= CMD_PRECHARGE;
+				sd_addr[10]		<= 1;
+				sd_bank_active	<= 0;
 			end else if (sd_auto_refresh) begin 
 				// while the cycle is active count.
 				sd_cycle <= sd_cycle + 3'd1;
@@ -179,7 +199,6 @@ always @(posedge sd_clk) begin
 				CYCLE_RFSH_START: begin 
 					sd_cmd	<= CMD_AUTO_REFRESH;
 				end
-
 				CYCLE_RFSH_END: begin 
 					// reset the count.
 					sd_auto_refresh <= 1'b0;
@@ -187,16 +206,29 @@ always @(posedge sd_clk) begin
 				end
 				endcase
 
-			end else if (sd_cyc | (sd_cycle != 0)) begin 
+			end else if (sd_cyc | (sd_cycle != 0) | (sd_cycle == 0 && sd_req)) begin 
 
 				// while the cycle is active count.
 				sd_cycle <= sd_cycle + 3'd1;
-				//sd_cmd		<= CMD_NOP;
 				case (sd_cycle)
+				CYCLE_PRECHARGE: begin
+					if (~sd_bank_active[sd_bank])
+						sd_cycle	<= CYCLE_RAS_START;
+					else if (sd_active_row[sd_bank] == sd_row)
+						sd_cycle	<= CYCLE_CAS0 - 1'd1; // FIXME: Why doesn't work without -1?
+					else begin
+						sd_cmd		<= CMD_PRECHARGE;
+						sd_addr[10] <= 0;
+						sd_ba		<= sd_bank;
+					end
+				end
+
 				CYCLE_RAS_START: begin 
 					sd_cmd 	<= CMD_ACTIVE;
-					sd_addr	<= { 1'b0, wb_adr[20:9] };
-					sd_ba 	<= wb_adr[22:21];
+					sd_addr	<= { 1'b0, sd_row };
+					sd_ba 	<= sd_bank;
+					sd_active_row[sd_bank] <= sd_row;
+					sd_bank_active[sd_bank] <= 1;
 
 					if(sd_reading) begin 
 						sd_dqm <= 2'b00;
@@ -210,29 +242,37 @@ always @(posedge sd_clk) begin
 					// always, always read on a 32bit boundary and completely ignore the lsb of wb_adr.
 					sd_addr <= { 4'b0000, wb_adr[23], wb_adr[8:2], 1'b0 };  // no auto precharge
 					sd_dqm		<= ~wb_sel[1:0];
+					sd_ba 	<= sd_bank;
 
 					if (sd_reading) begin 
 						sd_cmd <= CMD_READ;
 					end else if (sd_writing) begin 
 						sd_cmd		<= CMD_WRITE;
+`ifdef VERILATOR
+						sd_q		<= wb_dat_i[15:0];
+`else
 						sd_dq	 		<= wb_dat_i[15:0];
+`endif
 					end
 				end
 
 				CYCLE_CAS1: begin 
 					// now we access the second part of the 32 bit location.
-					sd_addr <= { 4'b0010, wb_adr[23], wb_adr[8:2], 1'b1 };  // auto precharge
+					sd_addr <= { 4'b0000, wb_adr[23], wb_adr[8:2], 1'b1 };  // no auto precharge
 					sd_dqm		<= ~wb_sel[3:2];
 					if (sd_reading) begin 
 						sd_cmd <= CMD_READ;
 						if (burst_mode & can_burst) begin 
-							sd_addr[10] <= 1'b0;
 							sd_burst <= 1'b1; 
 						end
 					end else if (sd_writing) begin 
 						sd_cmd		<= CMD_WRITE;
+						sd_done		<= ~sd_done;
+`ifdef VERILATOR
+						sd_q        <= wb_dat_i[31:16];
+`else
 						sd_dq 		<= wb_dat_i[31:16];
-						sd_done		<= 1'b1;
+`endif
 					end 
 				end
 				
@@ -250,7 +290,7 @@ always @(posedge sd_clk) begin
 				CYCLE_CAS3: begin 
 					if (sd_burst) begin 
 						// always, always read on a 32bit boundary and completely ignore the lsb of wb_adr.
-						sd_addr	<= { 4'b0010, wb_adr[23], wb_adr[8:3], 2'b11 };  // no auto precharge
+						sd_addr	<= { 4'b0000, wb_adr[23], wb_adr[8:3], 2'b11 };  // no auto precharge
 						sd_dqm	<= ~wb_sel[3:2];
 						if (sd_reading) begin 
 							sd_cmd <= CMD_READ;
@@ -259,23 +299,17 @@ always @(posedge sd_clk) begin
 				end
 
 				CYCLE_READ0: begin 
-					if (sd_writing) begin
-						// if we are writing then the sd_done signal has been high for 
-						// enough clock cycles. we can end the cycle here. 
-						sd_done <= 1'b0;
-						sd_cycle <= 4'd0;
-						sd_cyc <= 1'b0;
-						sd_stb <= 1'b0;
-					end
 					if (sd_reading) begin 
 					        sd_dat[15:0] <= sd_dq;
+					end else begin
+						if (sd_writing) sd_cycle <= CYCLE_END;
 					end 
 				end
 
 				CYCLE_READ1: begin 
 					if (sd_reading) begin 
 						sd_dat[31:16] <= sd_dq;
-						sd_done			<= 1'b1;
+						sd_done <= ~sd_done;
 					end
 				end
 
@@ -293,13 +327,11 @@ always @(posedge sd_clk) begin
 
 				CYCLE_END: begin 
 					sd_burst <= 1'b0;
-					sd_done 	<= 1'b0;
 					sd_cyc <= 1'b0;
 					sd_stb <= 1'b0;
 				end
 				endcase
 			end else begin
-				sd_done		<= 1'd0;
 				sd_cycle 	<= 4'd0;
 				sd_burst <= 1'b0;
 			end
@@ -309,9 +341,15 @@ end
 
 reg wb_burst;
 always @(posedge wb_clk) begin 
-	wb_ack <= sd_done & ~wb_ack;
+	reg sd_doneD;
+	
+	sd_doneD <= sd_done;
+	wb_ack	<= (sd_done ^ sd_doneD) & ~wb_ack;
+	
 	if (wb_stb & wb_cyc) begin 
-		if (sd_done & ~wb_ack) begin 
+	
+		if ((sd_done ^ sd_doneD) & ~wb_ack) begin 
+	
 			wb_dat_o <= sd_dat;
 			wb_burst <= burst_mode;
 		end
diff --git a/sys/pll.qip b/sys/pll.qip
index b08e56b..c43bdbb 100644
--- a/sys/pll.qip
+++ b/sys/pll.qip
@@ -41,11 +41,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTI4LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTI2LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTc=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::Mzk1MTM2OTgyNg==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MjA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::Njg3MTk0Njgx::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
@@ -53,11 +53,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTI4LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTI2LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTc=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::Mzk1MTM2OTgyNg==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MjA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::Njg3MTk0Njgx::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::LTQzNTA=::UGhhc2UgU2hpZnQ="
@@ -65,11 +65,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MzIuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NDIuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTc=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::Mzk1MTM2OTgyNg==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::Mjg=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MjA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::Njg3MTk0Njgx::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MjQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
@@ -79,9 +79,9 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::NTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTc=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::Mzk1MTM2ODAyMw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MTg=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
@@ -256,13 +256,13 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTI4LjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTI2LjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTI4LjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::LTQzMjQgcHM=::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTI2LjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::LTQzNDAgcHM=::cGhhc2Vfc2hpZnQx"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MzIuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NDIuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
@@ -318,7 +318,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::OSw4LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDQsMywxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDQsMyw0LDEscGhfbXV4X2NsayxmYWxzZSx0cnVlLDE0LDE0LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCw4OTUuOTk5OTk5IE1IeiwzOTUxMzY5ODI2LG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTAsMTAsMjU2LDI1NixmYWxzZSx0cnVlLGZhbHNlLGZhbHNlLDQsNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw0LDQsNCw1LHBoX211eF9jbGssZmFsc2UsZmFsc2UsMTIsMTIsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMSwyMCw0MDAwLDEwMDcuOTk5OTk5IE1Ieiw2ODcxOTQ2ODEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
diff --git a/sys/pll.v b/sys/pll.v
index d45b14c..e8e9cea 100644
--- a/sys/pll.v
+++ b/sys/pll.v
@@ -1,257 +1,257 @@
-// megafunction wizard: %Altera PLL v17.0%
-// GENERATION: XML
-// pll.v
-
-// Generated using ACDS version 17.0 602
-
-`timescale 1 ps / 1 ps
-module pll (
-		input  wire  refclk,   //  refclk.clk
-		input  wire  rst,      //   reset.reset
-		output wire  outclk_0, // outclk0.clk
-		output wire  outclk_1, // outclk1.clk
-		output wire  outclk_2, // outclk2.clk
-		output wire  locked    //  locked.export
-	);
-
-	pll_0002 pll_inst (
-		.refclk   (refclk),   //  refclk.clk
-		.rst      (rst),      //   reset.reset
-		.outclk_0 (outclk_0), // outclk0.clk
-		.outclk_1 (outclk_1), // outclk1.clk
-		.outclk_2 (outclk_2), // outclk2.clk
-		.locked   (locked)    //  locked.export
-	);
-
-endmodule
-// Retrieval info: <?xml version="1.0"?>
-//<!--
-//	Generated by Altera MegaWizard Launcher Utility version 1.0
-//	************************************************************
-//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//	************************************************************
-//	Copyright (C) 1991-2019 Altera Corporation
-//	Any megafunction design, and related net list (encrypted or decrypted),
-//	support information, device programming or simulation file, and any other
-//	associated documentation or information provided by Altera or a partner
-//	under Altera's Megafunction Partnership Program may be used only to
-//	program PLD devices (but not masked PLD devices) from Altera.  Any other
-//	use of such megafunction design, net list, support information, device
-//	programming or simulation file, or any other related documentation or
-//	information is prohibited for any other purpose, including, but not
-//	limited to modification, reverse engineering, de-compiling, or use with
-//	any other silicon devices, unless such use is explicitly licensed under
-//	a separate agreement with Altera or a megafunction partner.  Title to
-//	the intellectual property, including patents, copyrights, trademarks,
-//	trade secrets, or maskworks, embodied in any such megafunction design,
-//	net list, support information, device programming or simulation file, or
-//	any other related documentation or information provided by Altera or a
-//	megafunction partner, remains with Altera, the megafunction partner, or
-//	their respective licensors.  No other licenses, including any licenses
-//	needed under any third party's intellectual property, are provided herein.
-//-->
-// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
-// Retrieval info: 	<generic name="debug_print_output" value="false" />
-// Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
-// Retrieval info: 	<generic name="device_family" value="Cyclone V" />
-// Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
-// Retrieval info: 	<generic name="gui_device_speed_grade" value="2" />
-// Retrieval info: 	<generic name="gui_pll_mode" value="Fractional-N PLL" />
-// Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
-// Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
-// Retrieval info: 	<generic name="gui_operation_mode" value="direct" />
-// Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
-// Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
-// Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
-// Retrieval info: 	<generic name="gui_use_locked" value="true" />
-// Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
-// Retrieval info: 	<generic name="gui_number_of_clocks" value="3" />
-// Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
-// Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
-// Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
-// Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="128.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="128.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift1" value="-4350" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg1" value="180.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="32.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency3" value="50.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="48.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency5" value="8.333" />
-// Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency6" value="8.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
-// Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
-// Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
-// Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-// Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
-// Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
-// Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
-// Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
-// Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
-// Retrieval info: 	<generic name="gui_pll_auto_reset" value="On" />
-// Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
-// Retrieval info: 	<generic name="gui_en_reconf" value="false" />
-// Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
-// Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
-// Retrieval info: 	<generic name="gui_phout_division" value="1" />
-// Retrieval info: 	<generic name="gui_mif_generate" value="false" />
-// Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
-// Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
-// Retrieval info: 	<generic name="gui_dps_num" value="1" />
-// Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
-// Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
-// Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
-// Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
-// Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
-// Retrieval info: 	<generic name="gui_active_clk" value="false" />
-// Retrieval info: 	<generic name="gui_clk_bad" value="false" />
-// Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
-// Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
-// Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
-// Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-// Retrieval info: </instance>
-// IPFS_FILES : pll.vo
-// RELATED_FILES: pll.v, pll_0002.v
+// megafunction wizard: %Altera PLL v17.0%
+// GENERATION: XML
+// pll.v
+
+// Generated using ACDS version 17.0 602
+
+`timescale 1 ps / 1 ps
+module pll (
+		input  wire  refclk,   //  refclk.clk
+		input  wire  rst,      //   reset.reset
+		output wire  outclk_0, // outclk0.clk
+		output wire  outclk_1, // outclk1.clk
+		output wire  outclk_2, // outclk2.clk
+		output wire  locked    //  locked.export
+	);
+
+	pll_0002 pll_inst (
+		.refclk   (refclk),   //  refclk.clk
+		.rst      (rst),      //   reset.reset
+		.outclk_0 (outclk_0), // outclk0.clk
+		.outclk_1 (outclk_1), // outclk1.clk
+		.outclk_2 (outclk_2), // outclk2.clk
+		.locked   (locked)    //  locked.export
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2019 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
+// Retrieval info: 	<generic name="debug_print_output" value="false" />
+// Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
+// Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
+// Retrieval info: 	<generic name="gui_device_speed_grade" value="2" />
+// Retrieval info: 	<generic name="gui_pll_mode" value="Fractional-N PLL" />
+// Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
+// Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
+// Retrieval info: 	<generic name="gui_operation_mode" value="direct" />
+// Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
+// Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
+// Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
+// Retrieval info: 	<generic name="gui_use_locked" value="true" />
+// Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
+// Retrieval info: 	<generic name="gui_number_of_clocks" value="3" />
+// Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
+// Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="126.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="126.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift1" value="-4350" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg1" value="180.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="42.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency3" value="50.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="48.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency5" value="8.333" />
+// Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency6" value="8.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
+// Retrieval info: 	<generic name="gui_pll_auto_reset" value="On" />
+// Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
+// Retrieval info: 	<generic name="gui_en_reconf" value="false" />
+// Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
+// Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
+// Retrieval info: 	<generic name="gui_phout_division" value="1" />
+// Retrieval info: 	<generic name="gui_mif_generate" value="false" />
+// Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
+// Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
+// Retrieval info: 	<generic name="gui_dps_num" value="1" />
+// Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
+// Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
+// Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
+// Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+// Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
+// Retrieval info: 	<generic name="gui_active_clk" value="false" />
+// Retrieval info: 	<generic name="gui_clk_bad" value="false" />
+// Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
+// Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
+// Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
+// Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+// Retrieval info: </instance>
+// IPFS_FILES : pll.vo
+// RELATED_FILES: pll.v, pll_0002.v
diff --git a/sys/pll/pll_0002.v b/sys/pll/pll_0002.v
index b843c73..f99ca2a 100644
--- a/sys/pll/pll_0002.v
+++ b/sys/pll/pll_0002.v
@@ -1,93 +1,93 @@
-`timescale 1ns/10ps
-module  pll_0002(
-
-	// interface 'refclk'
-	input wire refclk,
-
-	// interface 'reset'
-	input wire rst,
-
-	// interface 'outclk0'
-	output wire outclk_0,
-
-	// interface 'outclk1'
-	output wire outclk_1,
-
-	// interface 'outclk2'
-	output wire outclk_2,
-
-	// interface 'locked'
-	output wire locked
-);
-
-	altera_pll #(
-		.fractional_vco_multiplier("true"),
-		.reference_clock_frequency("50.0 MHz"),
-		.operation_mode("direct"),
-		.number_of_clocks(3),
-		.output_clock_frequency0("128.000000 MHz"),
-		.phase_shift0("0 ps"),
-		.duty_cycle0(50),
-		.output_clock_frequency1("128.000000 MHz"),
-		.phase_shift1("-4324 ps"),
-		.duty_cycle1(50),
-		.output_clock_frequency2("32.000000 MHz"),
-		.phase_shift2("0 ps"),
-		.duty_cycle2(50),
-		.output_clock_frequency3("0 MHz"),
-		.phase_shift3("0 ps"),
-		.duty_cycle3(50),
-		.output_clock_frequency4("0 MHz"),
-		.phase_shift4("0 ps"),
-		.duty_cycle4(50),
-		.output_clock_frequency5("0 MHz"),
-		.phase_shift5("0 ps"),
-		.duty_cycle5(50),
-		.output_clock_frequency6("0 MHz"),
-		.phase_shift6("0 ps"),
-		.duty_cycle6(50),
-		.output_clock_frequency7("0 MHz"),
-		.phase_shift7("0 ps"),
-		.duty_cycle7(50),
-		.output_clock_frequency8("0 MHz"),
-		.phase_shift8("0 ps"),
-		.duty_cycle8(50),
-		.output_clock_frequency9("0 MHz"),
-		.phase_shift9("0 ps"),
-		.duty_cycle9(50),
-		.output_clock_frequency10("0 MHz"),
-		.phase_shift10("0 ps"),
-		.duty_cycle10(50),
-		.output_clock_frequency11("0 MHz"),
-		.phase_shift11("0 ps"),
-		.duty_cycle11(50),
-		.output_clock_frequency12("0 MHz"),
-		.phase_shift12("0 ps"),
-		.duty_cycle12(50),
-		.output_clock_frequency13("0 MHz"),
-		.phase_shift13("0 ps"),
-		.duty_cycle13(50),
-		.output_clock_frequency14("0 MHz"),
-		.phase_shift14("0 ps"),
-		.duty_cycle14(50),
-		.output_clock_frequency15("0 MHz"),
-		.phase_shift15("0 ps"),
-		.duty_cycle15(50),
-		.output_clock_frequency16("0 MHz"),
-		.phase_shift16("0 ps"),
-		.duty_cycle16(50),
-		.output_clock_frequency17("0 MHz"),
-		.phase_shift17("0 ps"),
-		.duty_cycle17(50),
-		.pll_type("General"),
-		.pll_subtype("General")
-	) altera_pll_i (
-		.rst	(rst),
-		.outclk	({outclk_2, outclk_1, outclk_0}),
-		.locked	(locked),
-		.fboutclk	( ),
-		.fbclk	(1'b0),
-		.refclk	(refclk)
-	);
-endmodule
-
+`timescale 1ns/10ps
+module  pll_0002(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'outclk2'
+	output wire outclk_2,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("true"),
+		.reference_clock_frequency("50.0 MHz"),
+		.operation_mode("direct"),
+		.number_of_clocks(3),
+		.output_clock_frequency0("126.000000 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("126.000000 MHz"),
+		.phase_shift1("-4340 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("42.000000 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_2, outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+