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https://github.com/MiSTer-devel/Archie_MiSTer.git
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add reset to cpu
added more regs to reset for other modules added simulation some changes to be standard conform, mostly reordering of wire/reg defines
This commit is contained in:
RobertPeip
GitHub
389
sim/stringprocessor.vhd
Normal file
389
sim/stringprocessor.vhd
Normal file
@@ -0,0 +1,389 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use STD.textio.all;
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use work.globals.all;
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entity estringprocessor is
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generic
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(
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clk_speed : integer := 50000000
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);
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port
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(
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ready : in std_logic;
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tx_command : out std_logic_vector(31 downto 0);
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tx_bytes : out integer range 0 to 4;
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tx_enable : out std_logic := '0';
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rx_command : in std_logic_vector(31 downto 0);
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rx_valid : in std_logic
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);
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end entity;
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architecture arch of estringprocessor is
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constant proc_busadr : integer := 28;
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constant proc_buswidth : integer := 32;
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constant clk_period : time := (1000000000 / clk_speed) * 1 ns;
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signal string_command : string(1 to 3);
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type t_internal_variables is array(0 to 256) of integer;
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signal internal_variables : t_internal_variables := (others => 0);
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type r_thread_record is record
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id : integer;
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waittime : integer;
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waitcommand : line;
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end record;
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type t_thread_buffers is array(0 to 255) of r_thread_record;
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procedure find_id
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(
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variable t_buf : inout t_thread_buffers;
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variable id : in integer;
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variable slot : out integer
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) is
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begin
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for i in 0 to 255 loop
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if (t_buf(i).id = id) then
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slot := i;
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exit;
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elsif (t_buf(i).id = -1) then
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t_buf(i).id := id;
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slot := i;
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exit;
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end if;
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end loop;
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end procedure;
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begin
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process
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file infile : text;
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file outfile : text;
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variable f_status : FILE_OPEN_STATUS;
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variable newdat : LINE;
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variable endfound : boolean;
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variable buf : LINE;
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variable run : boolean := true;
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variable line_out : line;
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variable debugline_out : line;
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variable command : string(1 to 3);
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variable dev_null_str3 : string (1 to 3);
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variable dev_null_str6 : string (1 to 6);
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variable OK : boolean := FALSE;
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variable para_int1 : integer;
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variable para_int2 : integer;
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variable para_int3 : integer;
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variable para_int4 : integer;
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variable address : integer;
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variable data : integer;
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variable count : integer;
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variable thread_buffers : t_thread_buffers := (others => (-1, 0, null));
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variable freerun : boolean := false;
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begin
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file_open(f_status, outfile, "input.txt", write_mode);
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file_close(outfile);
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file_open(f_status, outfile, "output.txt", write_mode);
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file_close(outfile);
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file_open(f_status, infile, "input.txt", read_mode);
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wait for 1000 ns;
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while (run) loop
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if not endfile(infile) then
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endfound := false;
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buf := null;
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while (endfound = false) loop
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if not endfile(infile) then
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readline(infile,newdat);
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for i in 1 to newdat'length loop
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write(buf, newdat(i to i));
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if (newdat(i to i) = "&") then
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endfound := true;
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end if;
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end loop;
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end if;
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end loop;
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command := buf(1 to 3);
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string_command <= command;
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line_out := null;
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buf(buf'length) := ' ';
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write(line_out, buf(1 to buf'length));
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write(line_out, string'("# "));
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if (command(1 to 3) = String'("set")) then
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-- command
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Read(buf, dev_null_str6);
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-- command nr
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Read(buf, para_int1, OK);
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Read(buf, dev_null_str3);
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-- process id
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Read(buf, para_int1, OK);
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Read(buf, dev_null_str3);
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-- target for reading
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Read(buf, para_int2, OK);
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Read(buf, dev_null_str3);
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-- count
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Read(buf, count, OK);
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Read(buf, dev_null_str3);
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-- address in target space
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Read(buf, address, OK);
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Read(buf, dev_null_str3);
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-- write address
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if (ready = '0') then
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wait until ready = '1';
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end if;
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tx_command <= "0000" & std_logic_vector(to_unsigned(address,proc_busadr));
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if (count > 1) then
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tx_command(31) <= '1';
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end if;
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tx_bytes <= 4;
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tx_enable <= '1';
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wait for clk_period*2;
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tx_enable <= '0';
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-- write block size
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if (count > 1) then
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if (ready = '0') then
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wait until ready = '1';
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end if;
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tx_command <= std_logic_vector(to_unsigned(count - 1,32));
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tx_bytes <= 4;
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tx_enable <= '1';
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wait for clk_period*2;
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tx_enable <= '0';
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end if;
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for i in 1 to count loop
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-- value to write
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Read(buf, data, OK);
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if (i < count) then
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Read(buf, dev_null_str3);
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end if;
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-- write data
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if (ready = '0') then
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wait until ready = '1';
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end if;
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tx_command <= std_logic_vector(to_signed(data,proc_buswidth));
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tx_bytes <= 4;
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tx_enable <= '1';
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wait for clk_period*2;
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tx_enable <= '0';
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wait for 20*clk_period; -- this is required, because there is no answer for write commands
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address := address + 1;
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end loop;
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write(line_out, string'("&"));
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file_open(f_status, outfile, "output.txt", append_mode);
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writeline(outfile, line_out);
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file_close(outfile);
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end if;
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if (command(1 to 3) = String'("get")) then
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-- command
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Read(buf, dev_null_str6);
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-- command nr
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Read(buf, para_int1, OK);
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Read(buf, dev_null_str3);
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-- process id
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Read(buf, para_int1, OK);
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Read(buf, dev_null_str3);
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-- target for reading
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Read(buf, para_int1, OK);
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Read(buf, dev_null_str3);
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-- count
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Read(buf, count, OK);
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Read(buf, dev_null_str3);
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-- address in target space
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Read(buf, address, OK);
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-- write address
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if (ready = '0') then
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wait until ready = '1';
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end if;
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tx_command <= "0100" & std_logic_vector(to_unsigned(address,proc_busadr));
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if (count > 1) then
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tx_command(31) <= '1';
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end if;
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tx_bytes <= 4;
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tx_enable <= '1';
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wait for clk_period*2;
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tx_enable <= '0';
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-- write block size
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if (count > 1) then
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if (ready = '0') then
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wait until ready = '1';
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end if;
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tx_command <= std_logic_vector(to_unsigned(count - 1,32));
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tx_bytes <= 4;
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tx_enable <= '1';
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wait for clk_period*2;
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tx_enable <= '0';
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end if;
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for i in 1 to count loop
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if (rx_valid = '0') then
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wait until rx_valid = '1';
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end if;
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data := to_integer(signed(rx_command(31 downto 0)));
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wait until rx_valid = '0';
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write(line_out, data);
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write(line_out, string'("#"));
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address := address + 1;
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end loop;
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write(line_out, string'("&"));
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file_open(f_status, outfile, "output.txt", append_mode);
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writeline(outfile, line_out);
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file_close(outfile);
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end if;
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if (command(1 to 3) = String'("fil")) then
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-- command
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Read(buf, dev_null_str6);
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-- command nr
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Read(buf, para_int1, OK);
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Read(buf, dev_null_str3);
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-- process id
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Read(buf, para_int1, OK);
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Read(buf, dev_null_str3);
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-- endianess
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Read(buf, para_int2, OK);
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Read(buf, dev_null_str3);
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-- address in target space
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Read(buf, address, OK);
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Read(buf, dev_null_str3);
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COMMAND_FILE_NAME <= (others => ' ');
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COMMAND_FILE_NAME(1 to buf'length) <= buf(1 to buf'length);
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COMMAND_FILE_NAMELEN <= buf'length;
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COMMAND_FILE_TARGET <= address;
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if (para_int2 = 1) then
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COMMAND_FILE_ENDIAN <= '1';
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else
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COMMAND_FILE_ENDIAN <= '0';
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end if;
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COMMAND_FILE_START <= '1';
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wait until COMMAND_FILE_ACK = '1';
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COMMAND_FILE_START <= '0';
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wait for 20 ns;
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write(line_out, string'("&"));
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file_open(f_status, outfile, "output.txt", append_mode);
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writeline(outfile, line_out);
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file_close(outfile);
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end if;
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if (command(1 to 3) = String'("brk")) then
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run := false;
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end if;
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if (command(1 to 3) = String'("wtn")) then
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-- command
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Read(buf, dev_null_str6);
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-- command nr
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Read(buf, para_int1, OK);
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Read(buf, dev_null_str3);
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-- process id
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Read(buf, para_int1, OK);
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Read(buf, dev_null_str3);
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-- time to wait
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Read(buf, para_int2, OK);
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write(line_out, string'("&"));
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if (para_int2 = -1) then
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freerun := true;
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find_id(thread_buffers, para_int1, para_int3);
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thread_buffers(para_int3).waittime := 2;
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thread_buffers(para_int3).waitcommand := line_out;
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else
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find_id(thread_buffers, para_int1, para_int3);
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thread_buffers(para_int3).waittime := para_int2;
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thread_buffers(para_int3).waitcommand := line_out;
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end if;
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end if;
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wait for 1 ps;
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end if;
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OK := false;
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for i in 0 to 255 loop
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if (thread_buffers(i).id /= -1) then
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if (thread_buffers(i).waittime = 1) then
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file_open(f_status, outfile, "output.txt", append_mode);
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writeline(outfile, thread_buffers(i).waitcommand);
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file_close(outfile);
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end if;
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if (thread_buffers(i).waittime > 0) then
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OK := true;
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thread_buffers(i).waittime := thread_buffers(i).waittime - 1;
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end if;
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end if;
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end loop;
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if (OK = true or freerun = true) then
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wait for 1 ns;
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end if;
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end loop;
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file_close(infile);
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wait;
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end process;
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end architecture;
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