From d27867c541e5ea64d610e149b0632b70ca47692f Mon Sep 17 00:00:00 2001 From: sorgelig Date: Fri, 18 May 2018 20:44:42 +0800 Subject: [PATCH] Tweak SDRAM timings. --- sys/sys_top.sdc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index 656d9c0..cff810d 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -28,8 +28,8 @@ set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -setup 2 -set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] -set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -max -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -min -clock SDRAM_CLK -1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] # Decouple different clock groups (to simplify routing) set_clock_groups -asynchronous \