From 702c9c7269ec4a359580cd577710c2dd0ddca618 Mon Sep 17 00:00:00 2001 From: sorgelig Date: Thu, 12 Sep 2019 22:53:17 +0800 Subject: [PATCH] Update sys. --- Archie.sv | 14 +++- sys/hdmi_config.sv | 18 ++-- sys/i2c.v | 201 +++++++++++++++++++++++++++++++++++---------- sys/mcp23009.sv | 114 +++++++++++++++++++++++++ sys/osd.v | 42 +++++----- sys/sys.qip | 1 + sys/sys.tcl | 37 ++++----- sys/sys_top.v | 105 +++++++++++++---------- 8 files changed, 393 insertions(+), 139 deletions(-) create mode 100644 sys/mcp23009.sv diff --git a/Archie.sv b/Archie.sv index e1c90f0..536a38d 100644 --- a/Archie.sv +++ b/Archie.sv @@ -59,6 +59,11 @@ module emu output [1:0] LED_POWER, output [1:0] LED_DISK, + // I/O board button press simulation (active high) + // b[1]: user button + // b[0]: osd button + output [1:0] BUTTONS, + output [15:0] AUDIO_L, output [15:0] AUDIO_R, output AUDIO_S, // 1 - signed audio samples, 0 - unsigned @@ -67,7 +72,7 @@ module emu //ADC inout [3:0] ADC_BUS, - // SD-SPI + //SD-SPI output SD_SCK, output SD_MOSI, input SD_MISO, @@ -110,10 +115,10 @@ module emu // Open-drain User port. // 0 - D+/RX // 1 - D-/TX - // 2..5 - USR1..USR4 + // 2..6 - USR2..USR6 // Set USER_OUT to 1 to read from USER_IN. - input [5:0] USER_IN, - output [5:0] USER_OUT, + input [6:0] USER_IN, + output [6:0] USER_OUT, input OSD_STATUS ); @@ -127,6 +132,7 @@ assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; assign LED_USER = 0; assign LED_DISK = 0; assign LED_POWER = 0; +assign BUTTONS = 0; assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4; assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3; diff --git a/sys/hdmi_config.sv b/sys/hdmi_config.sv index ab53841..20236e2 100644 --- a/sys/hdmi_config.sv +++ b/sys/hdmi_config.sv @@ -24,17 +24,19 @@ wire mI2C_ACK; reg [15:0] LUT_DATA; reg [7:0] LUT_INDEX = 0; -i2c #(50_000_000, 20_000) i2c_av +i2c_master #(50_000_000, 20_000) i2c_av ( - .CLK(iCLK), + .clk(iCLK), + .rst(~iRST_N), - .I2C_SCL(I2C_SCL), // I2C CLOCK - .I2C_SDA(I2C_SDA), // I2C DATA + .i2c_scl(I2C_SCL), // I2C CLOCK + .i2c_sda(I2C_SDA), // I2C DATA - .I2C_DATA({8'h72,init_data[LUT_INDEX]}), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]. 0x72 is the Slave Address of the ADV7513 chip! - .START(mI2C_GO), // START transfer - .END(mI2C_END), // END transfer - .ACK(mI2C_ACK) // ACK + .addr(8'h39), // 0x39 is the Slave Address of the ADV7513 chip + .data_in(init_data[LUT_INDEX]), + .start(mI2C_GO), // START transfer + .ready(mI2C_END), // END transfer + .error(mI2C_ACK) // ACK ); ////////////////////// Config Control //////////////////////////// diff --git a/sys/i2c.v b/sys/i2c.v index ace6293..7965f0e 100644 --- a/sys/i2c.v +++ b/sys/i2c.v @@ -1,68 +1,179 @@ - -module i2c +module i2c_master ( - input CLK, + input clk, + input rst, + input [6:0] addr, + input [15:0] data_in, + input start, + input rw, - input START, - input [23:0] I2C_DATA, - output reg END = 1, - output reg ACK = 0, + output reg error, + + output reg [7:0] data_out, + output reg ready, - //I2C bus - output I2C_SCL, - inout I2C_SDA + inout i2c_sda, + output i2c_scl ); - -// Clock Setting parameter CLK_Freq = 50_000_000; // 50 MHz parameter I2C_Freq = 400_000; // 400 KHz -reg I2C_CLOCK; -always@(negedge CLK) begin - integer mI2C_CLK_DIV = 0; - if(mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) begin - mI2C_CLK_DIV <= mI2C_CLK_DIV + 1; +localparam IDLE = 0; +localparam START = 1; +localparam ADDRESS = 2; +localparam READ_ACK = 3; +localparam WRITE_DATA = 4; +localparam WRITE_DATA2 = 5; +localparam WRITE_ACK = 6; +localparam READ_DATA = 7; +localparam READ_ACK2 = 8; +localparam READ_ACK3 = 9; +localparam STOP = 10; +localparam STOP2 = 11; + +localparam I2C_Rate = CLK_Freq/(I2C_Freq*2); + +assign i2c_scl = scl_disable | i2c_clk; +assign i2c_sda = ~sda_out ? 1'b0 : 1'bz; + +reg i2c_clk; +reg i2c_clk_d; +always@(posedge clk) begin + integer div = 0; + if(div < I2C_Rate) begin + div <= div + 1; end else begin - mI2C_CLK_DIV <= 0; - I2C_CLOCK <= ~I2C_CLOCK; + div <= 0; + i2c_clk <= ~i2c_clk; end + i2c_clk_d <= i2c_clk; end -assign I2C_SCL = SCLK | I2C_CLOCK; -assign I2C_SDA = SDO ? 1'bz : 1'b0; +reg sda_out = 1; +reg scl_disable = 0; -reg SCLK = 1, SDO = 1; +always @(posedge clk, posedge rst) begin + reg [3:0] state; + reg [7:0] saved_addr; + reg [7:0] saved_data1; + reg [7:0] saved_data2; + reg [2:0] counter; + reg old_st; -always @(posedge CLK) begin - reg old_clk; - reg old_st; + if(rst) begin + state <= IDLE; + scl_disable <= 1; + sda_out <= 1; + ready <= 0; + end + else begin + if(i2c_clk & ~i2c_clk_d) begin + old_st <= start; - reg [5:0] SD_COUNTER = 'b111111; - reg [0:31] SD; + case(state) + + IDLE: begin + ready <= 1; + if (~old_st & start) begin + state <= START; + saved_addr <= {addr, rw}; + {saved_data1,saved_data2} <= data_in; + error <= 0; + ready <= 0; + end + end - old_clk <= I2C_CLOCK; - old_st <= START; + START: begin + scl_disable <= 0; + counter <= 7; + state <= ADDRESS; + end - if(~old_st && START) begin - SCLK <= 1; - SDO <= 1; - ACK <= 0; - END <= 0; - SD <= {2'b10, I2C_DATA[23:16], 1'b1, I2C_DATA[15:8], 1'b1, I2C_DATA[7:0], 4'b1011}; - SD_COUNTER <= 0; - end else begin - if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin - SD_COUNTER <= SD_COUNTER + 6'd1; - case(SD_COUNTER) - 01: SCLK <= 0; - 10,19,28: ACK <= ACK | I2C_SDA; - 29: SCLK <= 1; - 32: END <= 1; + ADDRESS: begin + if (counter == 0) begin + state <= READ_ACK; + end else counter <= counter - 1'd1; + end + + READ_ACK: begin + if (i2c_sda == 0) begin + counter <= 7; + if(saved_addr[0] == 0) state <= WRITE_DATA; + else state <= READ_DATA; + end + else begin + state <= STOP; + error <= 1; + end + end + + WRITE_DATA: begin + if(counter == 0) begin + state <= READ_ACK2; + end else counter <= counter - 1'd1; + end + + READ_ACK2: begin + if (i2c_sda == 0) begin + state <= WRITE_DATA2; + counter <= 7; + end + else begin + state <= STOP; + error <= 1; + end + end + + WRITE_DATA2: begin + if(counter == 0) state <= READ_ACK3; + else counter <= counter - 1'd1; + end + + READ_ACK3: begin + if (i2c_sda == 0) state <= STOP; + else begin + state <= STOP; + error <= 1; + end + end + + READ_DATA: begin + data_out[counter] <= i2c_sda; + if (counter == 0) state <= WRITE_ACK; + else counter <= counter - 1'd1; + end + + WRITE_ACK: begin + state <= STOP; + end + + STOP: begin + scl_disable <= 1; + state <= STOP2; + end + + STOP2: begin + state <= IDLE; + end endcase end - if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO <= SD[SD_COUNTER[4:0]]; + if(~i2c_clk & i2c_clk_d) begin + case(state) + START: sda_out <= 0; + ADDRESS: sda_out <= saved_addr[counter]; + READ_ACK: sda_out <= 1; + READ_ACK2: sda_out <= 1; + READ_ACK3: sda_out <= 1; + WRITE_DATA: sda_out <= saved_data1[counter]; + WRITE_DATA2: sda_out <= saved_data2[counter]; + WRITE_ACK: sda_out <= 0; + READ_DATA: sda_out <= 1; + STOP: sda_out <= 0; + STOP2: sda_out <= 1; + endcase + end end end diff --git a/sys/mcp23009.sv b/sys/mcp23009.sv new file mode 100644 index 0000000..66c24e9 --- /dev/null +++ b/sys/mcp23009.sv @@ -0,0 +1,114 @@ +// +// MCP23009 +// (C) 2019 Alexey Melnikov +// +module mcp23009 +( + input clk, + + output reg [2:0] btn, + input [2:0] led, + output reg sd_cd, + + output scl, + inout sda +); + + +reg start = 0; +wire ready; +wire error; +reg rw; +wire [7:0] dout; +reg [15:0] din; + +i2c_master #(50_000_000, 500_000) i2c +( + .clk(clk), + .rst(0), + .addr('h20), + .data_in(din), + .start(start), + .rw(rw), + .error(error), + + .data_out(dout), + .ready(ready), + + .i2c_sda(sda), + .i2c_scl(scl) +); + +always@(posedge clk) begin + reg [3:0] idx = 0; + reg [1:0] state = 0; + reg [15:0] timeout = 0; + + if(~&timeout) begin + timeout <= timeout + 1'd1; + start <= 0; + state <= 0; + idx <= 0; + btn <= 0; + rw <= 0; + sd_cd <= 1; + end + else begin + if(~&init_data[idx]) begin + case(state) + 0: begin + start <= 1; + state <= 1; + din <= init_data[idx]; + end + 1: if(~ready) state <= 2; + 2: begin + start <= 0; + if(ready) begin + state <= 0; + if(!error) idx <= idx + 1'd1; + end + end + endcase + end + else begin + case(state) + 0: begin + start <= 1; + state <= 1; + din <= {8'h09,5'b00000,led}; + end + 1: if(~ready) state <= 2; + 2: begin + start <= 0; + if(ready) begin + state <= 0; + rw <= 0; + if(!error) begin + if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]}; + rw <= ~rw; + end + end + end + endcase + end + end +end + +wire [15:0] init_data[12] = +'{ + 16'h00F8, + 16'h0138, + 16'h0200, + 16'h0300, + 16'h0400, + 16'h0524, + 16'h06FF, + 16'h0700, + 16'h0800, + 16'h0900, + 16'h0A00, + 16'hFFFF +}; + +endmodule diff --git a/sys/osd.v b/sys/osd.v index 5c1fb04..f939102 100644 --- a/sys/osd.v +++ b/sys/osd.v @@ -143,6 +143,7 @@ always @(posedge clk_video) begin reg [21:0] osd_hcnt; reg osd_de1,osd_de2; reg [1:0] osd_en; + reg f1; if(ce_pix) begin @@ -168,28 +169,31 @@ always @(posedge clk_video) begin if(h_cnt > {dsp_width, 2'b00}) begin v_cnt <= 1; + f1 <= ~f1; // skip every other frame for interlace compatibility. + if(~f1) begin - osd_en <= (osd_en << 1) | osd_enable; - if(~osd_enable) osd_en <= 0; + osd_en <= (osd_en << 1) | osd_enable; + if(~osd_enable) osd_en <= 0; - if(v_cnt_below320) begin - multiscan <= 0; - v_osd_start <= info ? infoy : v_osd_start_320; - end - else if(v_cnt_below640) begin - multiscan <= 1; - v_osd_start <= info ? (infoy<<1) : v_osd_start_640; - end - else if(v_cnt_below960) begin - multiscan <= 2; - v_osd_start <= info ? (infoy + (infoy << 1)) : v_osd_start_960; - end - else begin - multiscan <= 3; - v_osd_start <= info ? (infoy<<2) : v_osd_start_other; + if(v_cnt_below320) begin + multiscan <= 0; + v_osd_start <= info ? infoy : v_osd_start_320; + end + else if(v_cnt_below640) begin + multiscan <= 1; + v_osd_start <= info ? (infoy<<1) : v_osd_start_640; + end + else if(v_cnt_below960) begin + multiscan <= 2; + v_osd_start <= info ? (infoy + (infoy << 1)) : v_osd_start_960; + end + else begin + multiscan <= 3; + v_osd_start <= info ? (infoy<<2) : v_osd_start_other; + end end end - + osd_div <= osd_div + 1'd1; if(osd_div == multiscan) begin osd_div <= 0; @@ -211,7 +215,7 @@ assign dout = rdout; reg [23:0] osd_rdout, normal_rdout; reg osd_mux; reg de_dly; - + always @(posedge clk_video) begin normal_rdout <= din; osd_rdout <= {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},// 23:16 diff --git a/sys/sys.qip b/sys/sys.qip index a67123e..6a5d6b6 100644 --- a/sys/sys.qip +++ b/sys/sys.qip @@ -19,6 +19,7 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ] diff --git a/sys/sys.tcl b/sys/sys.tcl index d976d0e..8e68170 100644 --- a/sys/sys.tcl +++ b/sys/sys.tcl @@ -19,16 +19,23 @@ set_location_assignment PIN_AD4 -to ADC_SDO #============================================================ # ARDUINO #============================================================ -set_location_assignment PIN_AG9 -to ARDUINO_IO[3] -set_location_assignment PIN_U14 -to ARDUINO_IO[4] -set_location_assignment PIN_U13 -to ARDUINO_IO[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*] set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*] +#============================================================ +# I2C LEDS/BUTTONS +#============================================================ +set_location_assignment PIN_U14 -to IO_SCL +set_location_assignment PIN_AG9 -to IO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IO_S* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IO_S* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to IO_S* + #============================================================ # USER PORT #============================================================ +set_location_assignment PIN_AF17 -to USER_IO[6] set_location_assignment PIN_AF15 -to USER_IO[5] set_location_assignment PIN_AG16 -to USER_IO[4] set_location_assignment PIN_AH11 -to USER_IO[3] @@ -43,9 +50,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO # SDIO_CD or SPDIF_OUT #============================================================ set_location_assignment PIN_AH7 -to SDCD_SPDIF - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCD_SPDIF - set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCD_SPDIF set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDCD_SPDIF @@ -67,7 +72,6 @@ set_location_assignment PIN_AD17 -to SDRAM_A[11] set_location_assignment PIN_D12 -to SDRAM_A[12] set_location_assignment PIN_Y17 -to SDRAM_BA[0] set_location_assignment PIN_AB25 -to SDRAM_BA[1] - set_location_assignment PIN_E8 -to SDRAM_DQ[0] set_location_assignment PIN_V12 -to SDRAM_DQ[1] set_location_assignment PIN_D11 -to SDRAM_DQ[2] @@ -86,10 +90,8 @@ set_location_assignment PIN_AF4 -to SDRAM_DQ[14] set_location_assignment PIN_AH3 -to SDRAM_DQ[15] set_location_assignment PIN_AG13 -to SDRAM_DQML set_location_assignment PIN_AF13 -to SDRAM_DQMH - set_location_assignment PIN_AD20 -to SDRAM_CLK set_location_assignment PIN_AG10 -to SDRAM_CKE - set_location_assignment PIN_AA19 -to SDRAM_nWE set_location_assignment PIN_AA18 -to SDRAM_nCAS set_location_assignment PIN_Y18 -to SDRAM_nCS @@ -106,18 +108,15 @@ set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* #============================================================ -# I/O #2 +# SPI SD #============================================================ -set_location_assignment PIN_AG8 -to BTNLED[0] -set_location_assignment PIN_AH8 -to BTNLED[1] -set_location_assignment PIN_AF17 -to BTNLED[2] -set_location_assignment PIN_AE15 -to BTNLED[3] - -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to BTNLED[*] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTNLED[*] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to BTNLED[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BTNLED[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTNLED[*] +set_location_assignment PIN_AE15 -to SD_SPI_CS +set_location_assignment PIN_AH8 -to SD_SPI_MISO +set_location_assignment PIN_AG8 -to SD_SPI_CLK +set_location_assignment PIN_U13 -to SD_SPI_MOSI +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI* #============================================================ diff --git a/sys/sys_top.v b/sys/sys_top.v index 1ceb931..42899c9 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -96,8 +96,14 @@ module sys_top `endif ////////// I/O ALT ///////// - inout [3:0] BTNLED, + output SD_SPI_CS, + input SD_SPI_MISO, + output SD_SPI_CLK, + output SD_SPI_MOSI, + inout SDCD_SPDIF, + inout IO_SCL, + inout IO_SDA, ////////// ADC ////////////// output ADC_SCK, @@ -115,21 +121,30 @@ module sys_top output [7:0] LED, ///////// USER IO /////////// - inout [5:0] USER_IO + inout [6:0] USER_IO ); ////////////////////// Secondary SD /////////////////////////////////// -`ifndef DUAL_SDRAM - wire SD_CS, SD_CLK, SD_MOSI, SD_MISO; +wire sd_miso; +wire SD_CS, SD_CLK, SD_MOSI, SD_MISO; +`ifndef DUAL_SDRAM assign SDIO_DAT[2:1]= 2'bZZ; assign SDIO_DAT[3] = SW[3] ? 1'bZ : SD_CS; assign SDIO_CLK = SW[3] ? 1'bZ : SD_CLK; assign SDIO_CMD = SW[3] ? 1'bZ : SD_MOSI; - assign SD_MISO = SW[3] ? 1'b1 : SDIO_DAT[0]; + assign sd_miso = SW[3] ? 1'b1 : SDIO_DAT[0]; + assign SD_SPI_CS = mcp_sdcd ? ((~VGA_EN & sog & ~cs1) ? 1'b1 : 1'bZ) : SD_CS; +`else + assign sd_miso = 1'b1; + assign SD_SPI_CS = mcp_sdcd ? 1'bZ : SD_CS; `endif +assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK; +assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI; +assign SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO; + ////////////////////// LEDs/Buttons /////////////////////////////////// reg [7:0] led_overtake = 0; @@ -149,33 +164,27 @@ wire led_locked; //LEDs on main board assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}); -reg [3:0] btnled = 3'bZZZ; -reg btn_r = 0, btn_o = 0, btn_u = 0; -always @(posedge FPGA_CLK2_50) begin - reg [12:0] cnt; - - if(SW[3]) begin - cnt <= cnt + 1'd1; - if(~&cnt[12:8]) btnled <= ~{1'b0,led_p,led_d,led_u}; - else begin - if(~cnt[7]) btnled <= 0; - else btnled <= 4'b0ZZZ; - if(&cnt) {btn_r,btn_o,btn_u} <= ~BTNLED[2:0]; - end - end - else begin - cnt <= 0; +wire btn_r, btn_o, btn_u; `ifdef DUAL_SDRAM - {btn_r,btn_o,btn_u} <= 0; - btnled <= 4'bZZZZ; + assign {btn_r,btn_o,btn_u} = {mcp_btn[1],mcp_btn[2],mcp_btn[0]}; `else - {btn_r,btn_o,btn_u} <= ~{BTN_RESET,BTN_OSD,BTN_USER}; - btnled <= {(~VGA_EN & sog & ~cs1) ? 1'b1 : 1'bZ, 3'bZZZ}; + assign {btn_r,btn_o,btn_u} = ~{BTN_RESET,BTN_OSD,BTN_USER} | {mcp_btn[1],mcp_btn[2],mcp_btn[0]}; `endif - end -end -assign BTNLED = btnled; +wire [2:0] mcp_btn; +wire mcp_sdcd; +mcp23009 mcp23009 +( + .clk(FPGA_CLK2_50), + + .btn(mcp_btn), + .led({led_p, led_d, led_u}), + .sd_cd(mcp_sdcd), + + .scl(IO_SCL), + .sda(IO_SDA) +); + reg btn_user, btn_osd; always @(posedge FPGA_CLK2_50) begin @@ -202,7 +211,7 @@ end // gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode) // used to avoid lockups while JTAG loading -wire [31:0] gp_in = {1'b0, btn_user, btn_osd, 9'd0, io_ver, io_ack, io_wide, io_dout}; +wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], SW[3], 8'd0, io_ver, io_ack, io_wide, io_dout}; wire [31:0] gp_out; wire [1:0] io_ver = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future. @@ -252,18 +261,18 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp reg [15:0] cfg; -reg cfg_got = 0; -reg cfg_set = 0; +reg cfg_got = 0; +reg cfg_set = 0; wire [1:0] hdmi_limited = {cfg[11],cfg[8]}; -wire dvi_mode = cfg[7]; -wire audio_96k = cfg[6]; -wire direct_video = cfg[10]; -wire csync_en = cfg[3]; -wire ypbpr_en = cfg[5]; -wire io_osd_vga= io_ss1 & ~io_ss2; +wire direct_video = cfg[10]; +wire dvi_mode = cfg[7]; +wire audio_96k = cfg[6]; +wire csync_en = cfg[3]; +wire ypbpr_en = cfg[5]; +wire io_osd_vga = io_ss1 & ~io_ss2; `ifndef DUAL_SDRAM - wire sog = cfg[9]; - wire vga_scaler= 1; //cfg[2]; + wire sog = cfg[9]; + wire vga_scaler = 1; // cfg[2]; `endif reg cfg_custom_t = 0; @@ -432,7 +441,7 @@ always @(posedge FPGA_CLK2_50) begin end wire clk_100m; -wire clk_hdmi = hdmi_tx_clk; +wire clk_hdmi = ~hdmi_tx_clk; // Internal HDMI clock, inverted in relation to external clock wire clk_audio = FPGA_CLK3_50; wire clk_pal = FPGA_CLK3_50; @@ -919,7 +928,7 @@ csync csync_vga(clk_vid, hs, vs, cs); ///////////////////////// Audio output //////////////////////////////// -assign SDCD_SPDIF =(SW[3] & spdif) ? 1'b0 : 1'bZ; +assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ; `ifndef DUAL_SDRAM wire anl,anr; @@ -1021,6 +1030,7 @@ assign USER_IO[2] = !(SW[1] ? HDMI_I2S : user_out[2]) ? 1'b0 : 1'bZ; assign USER_IO[3] = !user_out[3] ? 1'b0 : 1'bZ; assign USER_IO[4] = !(SW[1] ? HDMI_SCLK : user_out[4]) ? 1'b0 : 1'bZ; assign USER_IO[5] = !(SW[1] ? HDMI_LRCLK : user_out[5]) ? 1'b0 : 1'bZ; +assign USER_IO[6] = !user_out[6] ? 1'b0 : 1'bZ; assign user_in[0] = USER_IO[0]; assign user_in[1] = USER_IO[1]; @@ -1028,6 +1038,7 @@ assign user_in[2] = SW[1] | USER_IO[2]; assign user_in[3] = USER_IO[3]; assign user_in[4] = SW[1] | USER_IO[4]; assign user_in[5] = SW[1] | USER_IO[5]; +assign user_in[6] = USER_IO[6]; /////////////////// User module connection //////////////////////////// @@ -1054,6 +1065,7 @@ wire ram_write; wire led_user; wire [1:0] led_power; wire [1:0] led_disk; +wire [1:0] btn; wire vs_emu, hs_emu; sync_fix sync_v(clk_vid, vs_emu, vs); @@ -1067,7 +1079,7 @@ wire uart_rxd; wire uart_txd; wire osd_status; -wire [5:0] user_out, user_in; +wire [6:0] user_out, user_in; emu emu ( @@ -1090,6 +1102,7 @@ emu emu .LED_USER(led_user), .LED_POWER(led_power), .LED_DISK(led_disk), + .BUTTONS(btn), .VIDEO_ARX(ARX), .VIDEO_ARY(ARY), @@ -1134,12 +1147,16 @@ emu emu .SDRAM2_nCAS(SDRAM2_nCAS), .SDRAM2_CLK(SDRAM2_CLK), .SDRAM2_EN(SW[3]), -`else +`endif + .SD_SCK(SD_CLK), .SD_MOSI(SD_MOSI), .SD_MISO(SD_MISO), .SD_CS(SD_CS), - .SD_CD(SW[0] ? VGA_HS : SW[3] ? 1'b1 : SDCD_SPDIF ), +`ifdef DUAL_SDRAM + .SD_CD(mcp_sdcd), +`else + .SD_CD(mcp_sdcd & (SW[0] ? VGA_HS : (SW[3] | SDCD_SPDIF))), `endif .UART_CTS(uart_rts),