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96 lines
1.2 KiB
VHDL
96 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all,ieee.numeric_std.all;
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entity gray_code is
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port (
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clk : in std_logic;
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addr : in std_logic_vector(5 downto 0);
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data : out std_logic_vector(5 downto 0)
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);
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end entity;
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architecture prom of gray_code is
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type rom is array(0 to 63) of std_logic_vector(5 downto 0);
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signal rom_data: rom := (
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"000000",
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"000001",
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"000011",
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"000010",
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"000110",
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"000111",
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"000101",
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"000100",
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"001100",
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"001101",
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"001111",
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"001110",
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"001010",
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"001011",
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"001001",
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"001000",
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"011000",
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"011001",
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"011011",
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"011010",
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"011110",
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"011111",
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"011101",
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"011100",
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"010100",
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"010101",
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"010111",
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"010110",
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"010010",
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"010011",
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"010001",
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"010000",
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"110000",
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"110001",
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"110011",
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"110010",
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"110110",
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"110111",
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"110101",
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"110100",
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"111100",
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"111101",
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"111111",
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"111110",
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"111010",
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"111011",
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"111001",
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"111000",
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"101000",
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"101001",
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"101011",
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"101010",
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"101110",
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"101111",
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"101101",
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"101100",
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"100100",
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"100101",
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"100111",
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"100110",
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"100010",
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"100011",
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"100001",
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"100000"
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);
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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data <= rom_data(to_integer(unsigned(addr)));
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end if;
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end process;
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end architecture;
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