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87 lines
2.3 KiB
Verilog
87 lines
2.3 KiB
Verilog
/*
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* Copyright (c) 2014 Greg Taylor <gtaylor@sonic.net>
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*
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* This file is part of OPL3 FPGA.
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*
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* OPL3 FPGA is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* OPL3 FPGA is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with OPL3 FPGA. If not, see <http://www.gnu.org/licenses/>.
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*
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* Original Java Code:
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* Copyright (c) 2008 Robson Cozendey <robson@cozendey.com>
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*
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* Original C++ Code:
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* Copyright (c) 2012 Steffen Ohrendorf <steffen.ohrendorf@gmx.de>
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*
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* Some code based on forum posts in:
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* http://forums.submarine.org.uk/phpBB/viewforum.php?f=9,
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* Copyright (c) 2010-2013 by carbon14 and opl3
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*
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* Converted to Verilog and reduced to the OPL2 subset:
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* Copyright (c) 2018 Magnus Karlsson <magnus@saanlima.com>
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*
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* Fixed and refactored:
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* Copyright (c) 2020 Josh Bassett
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*/
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`timescale 1ns / 1ps
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`include "opl.vh"
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module timer #(
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parameter MAX_VALUE // ticks
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) (
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input wire clk,
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input wire [`REG_TIMER_WIDTH-1:0] init,
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input wire start,
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output reg overflow
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);
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reg [`REG_TIMER_WIDTH-1:0] counter = 0;
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reg [`CLOG2(MAX_VALUE)-1:0] sub_counter = 0;
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/*
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* Detect when start is initially set, use it to reset the timer value back
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* to the initial value. Also if start is not set clock will not run.
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*/
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opl_edge_detector #(
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.EDGE_LEVEL(1),
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.CLK_DLY(1)
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) start_timer_edge_detect (
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.clk(clk),
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.clk_en(1'b1),
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.in(start),
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.edge_detected(start_pulse)
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);
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/*
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* Timer gets set to init upon overflow
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*/
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always @(posedge clk) begin
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overflow <= 0;
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if (start_pulse) begin
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counter <= init;
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sub_counter <= MAX_VALUE - 1;
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end else if (start) begin
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sub_counter <= sub_counter - 1;
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if (!sub_counter) begin
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sub_counter <= MAX_VALUE - 1;
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counter <= counter + 1;
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if (&counter) begin
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overflow <= 1;
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counter <= init;
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end
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end
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end
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end
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endmodule
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