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202 lines
2.7 KiB
Verilog
202 lines
2.7 KiB
Verilog
// Copyright (c) 2014 MiSTer-X
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module VDPRAM400x2
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(
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input CL0,
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input [10:0] AD0,
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input WR0,
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input [7:0] WD0,
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output [7:0] RD0,
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input CL1,
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input [9:0] AD1,
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output [15:0] RD1
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);
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reg A10;
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always @( posedge CL0 ) A10 <= AD0[10];
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wire [7:0] RD00, RD01;
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DPRAM400 LS( CL0, AD0[9:0], WR0 & (~AD0[10]), WD0, RD00, CL1, AD1, 1'b0, 8'h0, RD1[15:8] );
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DPRAM400 HS( CL0, AD0[9:0], WR0 & ( AD0[10]), WD0, RD01, CL1, AD1, 1'b0, 8'h0, RD1[ 7:0] );
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assign RD0 = A10 ? RD01 : RD00;
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endmodule
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module PALETRAM
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(
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input CL0,
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input [8:0] AD0,
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input WR0,
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input [7:0] WD0,
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output [7:0] RD0,
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input CL1,
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input [7:0] AD1,
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output [15:0] RD1
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);
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reg A0;
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always @( posedge CL0 ) A0 <= AD0[0];
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wire [7:0] RD00, RD01;
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DPRAM100 LS( CL0, AD0[8:1], WR0 & (~AD0[0]), WD0, RD00, CL1, AD1, 1'b0, 8'h0, RD1[ 7:0] );
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DPRAM100 HS( CL0, AD0[8:1], WR0 & ( AD0[0]), WD0, RD01, CL1, AD1, 1'b0, 8'h0, RD1[15:8] );
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assign RD0 = A0 ? RD01 : RD00;
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endmodule
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module DPRAM400
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(
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input CL0,
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input [9:0] AD0,
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input WE0,
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input [7:0] WD0,
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output reg [7:0] RD0,
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input CL1,
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input [9:0] AD1,
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input WE1,
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input [7:0] WD1,
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output reg [7:0] RD1
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);
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reg [7:0] core[0:1023];
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always @( posedge CL0 ) begin
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if (WE0) core[AD0] <= WD0;
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RD0 <= core[AD0];
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end
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always @( posedge CL1 ) begin
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if (WE1) core[AD1] <= WD1;
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RD1 <= core[AD1];
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end
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endmodule
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module DPRAM100
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(
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input CL0,
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input [7:0] AD0,
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input WE0,
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input [7:0] WD0,
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output reg [7:0] RD0,
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input CL1,
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input [7:0] AD1,
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input WE1,
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input [7:0] WD1,
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output reg [7:0] RD1
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);
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reg [7:0] core[0:255];
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always @( posedge CL0 ) begin
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if (WE0) core[AD0] <= WD0;
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RD0 <= core[AD0];
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end
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always @( posedge CL1 ) begin
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if (WE1) core[AD1] <= WD1;
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RD1 <= core[AD1];
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end
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endmodule
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module VDPRAM80
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(
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input CL0,
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input [6:0] AD0,
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input WE0,
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input [7:0] WD0,
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output [7:0] RD0,
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input CL1,
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input [6:0] AD1,
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output [7:0] RD1
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);
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reg [7:0] core[0:127];
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always @( posedge CL0 ) begin
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if (WE0) core[AD0] <= WD0;
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end
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assign RD0 = core[AD0];
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assign RD1 = core[AD1];
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endmodule
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module RAM1000
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(
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input CL,
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input [11:0] AD,
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input WR,
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input [7:0] ID,
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output [7:0] OD
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);
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reg [7:0] core[0:4095];
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always @( posedge CL ) begin
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if (WR) core[AD] <= ID;
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end
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assign OD = core[AD];
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endmodule
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module RAM800
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(
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input CL,
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input [10:0] AD,
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input WR,
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input [7:0] ID,
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output [7:0] OD
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);
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reg [7:0] core[0:2047];
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always @( posedge CL ) begin
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if (WR) core[AD] <= ID;
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end
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assign OD = core[AD];
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endmodule
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module LineDBuf
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(
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input rC,
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input [9:0] rA,
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output [6:0] rD,
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input rE,
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input wC,
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input [9:0] wA,
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input [6:0] wD,
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input wE
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);
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DPRAM1024_7 core(
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rA,wA,
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rC,wC,
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7'd0,wD,
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rE,wE,
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rD
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);
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endmodule
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