mirror of
https://github.com/MiSTer-devel/Arcade-SolomonsKey_MiSTer.git
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146 lines
2.7 KiB
Verilog
146 lines
2.7 KiB
Verilog
// Copyright (c) 2014,19 MiSTer-X
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module MAINROM
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(
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input CL,
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input [15:0] AD,
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output [7:0] DT,
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output DV,
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input DLCL,
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input [19:0] DLAD,
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input [7:0] DLDT,
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input DLEN
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);
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/*
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34000-37FFF MAINCPU0
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38000-3FFFF MAINCPU1 (4000h swaped)
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40000-40FFF MAINCPU2
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*/
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wire [7:0] dt0, dt1, dt2, dt3;
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DLROM #(14,8) r0( CL, AD[13:0], dt0, DLCL,DLAD,DLDT,DLEN & (DLAD[19:14]==6'b0011_01) );
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DLROM #(14,8) r1( CL, AD[13:0], dt1, DLCL,DLAD,DLDT,DLEN & (DLAD[19:14]==6'b0011_11) );
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DLROM #(14,8) r2( CL, AD[13:0], dt2, DLCL,DLAD,DLDT,DLEN & (DLAD[19:14]==6'b0011_10) );
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DLROM #(12,8) r3( CL, AD[11:0], dt3, DLCL,DLAD,DLDT,DLEN & (DLAD[19:12]==8'b0100_0000) );
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wire dv0 = (AD[15:14]==2'b00);
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wire dv4 = (AD[15:14]==2'b01);
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wire dv8 = (AD[15:14]==2'b10);
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wire dvF = (AD[15:12]==4'b1111);
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assign DT = dvF ? dt3 :
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dv8 ? dt2 :
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dv4 ? dt1 :
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dv0 ? dt0 : 8'h0;
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assign DV = dvF|dv8|dv4|dv0;
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endmodule
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module FGROM
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(
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input CL,
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input [15:0] AD,
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output [7:0] DT,
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input DLCL,
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input [19:0] DLAD,
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input [7:0] DLDT,
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input DLEN
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);
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/*
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10000-17FFF FGCHIP0
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18000-1FFFF FGCHIP1
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*/
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DLROM #(16,8) r(CL,AD,DT, DLCL,DLAD,DLDT,DLEN & (DLAD[19:16]==4'd1) );
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endmodule
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module BGROM
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(
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input CL,
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input [15:0] AD,
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output [7:0] DT,
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input DLCL,
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input [19:0] DLAD,
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input [7:0] DLDT,
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input DLEN
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);
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/*
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20000-27FFF BGCHIP0
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28000-2FFFF BGCHIP1
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*/
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DLROM #(16,8) r(CL,AD,DT, DLCL,DLAD,DLDT,DLEN & (DLAD[19:16]==4'd2) );
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endmodule
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module SPROM
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(
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input CL,
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input [13:0] AD,
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output [31:0] DT,
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input DLCL,
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input [19:0] DLAD,
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input [7:0] DLDT,
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input DLEN
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);
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/*
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00000-03FFF SPCHIP0
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04000-07FFF SPCHIP1
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08000-0BFFF SPCHIP2
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0C000-0FFFF SPCHIP3
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*/
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wire [7:0] dt0,dt1,dt2,dt3;
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DLROM #(14,8) r0( CL, AD, dt0, DLCL,DLAD,DLDT,DLEN & (DLAD[19:14]==6'b0000_00) );
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DLROM #(14,8) r1( CL, AD, dt1, DLCL,DLAD,DLDT,DLEN & (DLAD[19:14]==6'b0000_01) );
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DLROM #(14,8) r2( CL, AD, dt2, DLCL,DLAD,DLDT,DLEN & (DLAD[19:14]==6'b0000_10) );
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DLROM #(14,8) r3( CL, AD, dt3, DLCL,DLAD,DLDT,DLEN & (DLAD[19:14]==6'b0000_11) );
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assign DT = {dt3,dt2,dt1,dt0};
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endmodule
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module SNDROM
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(
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input CL,
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input [13:0] AD,
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output [7:0] DT,
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input DLCL,
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input [19:0] DLAD,
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input [7:0] DLDT,
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input DLEN
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);
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// 30000-33FFF SNDCPU
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DLROM #(14,8) r(CL,AD,DT, DLCL,DLAD,DLDT,DLEN & (DLAD[19:14]==6'b0011_00));
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endmodule
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module DLROM #(parameter AW,parameter DW)
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(
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input CL0,
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input [(AW-1):0] AD0,
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output reg [(DW-1):0] DO0,
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input CL1,
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input [(AW-1):0] AD1,
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input [(DW-1):0] DI1,
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input WE1
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);
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reg [(DW-1):0] core[0:((2**AW)-1)];
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always @(posedge CL0) DO0 <= core[AD0];
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always @(posedge CL1) if (WE1) core[AD1] <= DI1;
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endmodule
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