mirror of
https://github.com/MiSTer-devel/Arcade-SolomonsKey_MiSTer.git
synced 2026-04-19 03:03:20 +00:00
431 lines
10 KiB
Systemverilog
431 lines
10 KiB
Systemverilog
//============================================================================
|
|
// Arcade: Solomon's Key
|
|
//
|
|
// Original implimentation and port to MiSTer by MiSTer-X 2019
|
|
//============================================================================
|
|
|
|
|
|
module emu
|
|
(
|
|
//Master input clock
|
|
input CLK_50M,
|
|
|
|
//Async reset from top-level module.
|
|
//Can be used as initial reset.
|
|
input RESET,
|
|
|
|
//Must be passed to hps_io module
|
|
inout [48:0] HPS_BUS,
|
|
|
|
//Base video clock. Usually equals to CLK_SYS.
|
|
output CLK_VIDEO,
|
|
|
|
//Multiple resolutions are supported using different CE_PIXEL rates.
|
|
//Must be based on CLK_VIDEO
|
|
output CE_PIXEL,
|
|
|
|
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
|
|
//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
|
|
output [12:0] VIDEO_ARX,
|
|
output [12:0] VIDEO_ARY,
|
|
|
|
output [7:0] VGA_R,
|
|
output [7:0] VGA_G,
|
|
output [7:0] VGA_B,
|
|
output VGA_HS,
|
|
output VGA_VS,
|
|
output VGA_DE, // = ~(VBlank | HBlank)
|
|
output VGA_F1,
|
|
output [1:0] VGA_SL,
|
|
output VGA_SCALER, // Force VGA scaler
|
|
output VGA_DISABLE, // analog out is off
|
|
|
|
input [11:0] HDMI_WIDTH,
|
|
input [11:0] HDMI_HEIGHT,
|
|
output HDMI_FREEZE,
|
|
output HDMI_BLACKOUT,
|
|
output HDMI_BOB_DEINT,
|
|
|
|
`ifdef MISTER_FB
|
|
// Use framebuffer in DDRAM
|
|
// FB_FORMAT:
|
|
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
|
|
// [3] : 0=16bits 565 1=16bits 1555
|
|
// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
|
|
//
|
|
// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
|
|
output FB_EN,
|
|
output [4:0] FB_FORMAT,
|
|
output [11:0] FB_WIDTH,
|
|
output [11:0] FB_HEIGHT,
|
|
output [31:0] FB_BASE,
|
|
output [13:0] FB_STRIDE,
|
|
input FB_VBL,
|
|
input FB_LL,
|
|
output FB_FORCE_BLANK,
|
|
|
|
`ifdef MISTER_FB_PALETTE
|
|
// Palette control for 8bit modes.
|
|
// Ignored for other video modes.
|
|
output FB_PAL_CLK,
|
|
output [7:0] FB_PAL_ADDR,
|
|
output [23:0] FB_PAL_DOUT,
|
|
input [23:0] FB_PAL_DIN,
|
|
output FB_PAL_WR,
|
|
`endif
|
|
`endif
|
|
|
|
output LED_USER, // 1 - ON, 0 - OFF.
|
|
|
|
// b[1]: 0 - LED status is system status OR'd with b[0]
|
|
// 1 - LED status is controled solely by b[0]
|
|
// hint: supply 2'b00 to let the system control the LED.
|
|
output [1:0] LED_POWER,
|
|
output [1:0] LED_DISK,
|
|
|
|
// I/O board button press simulation (active high)
|
|
// b[1]: user button
|
|
// b[0]: osd button
|
|
output [1:0] BUTTONS,
|
|
|
|
input CLK_AUDIO, // 24.576 MHz
|
|
output [15:0] AUDIO_L,
|
|
output [15:0] AUDIO_R,
|
|
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
|
|
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
|
|
|
|
//ADC
|
|
inout [3:0] ADC_BUS,
|
|
|
|
//SD-SPI
|
|
output SD_SCK,
|
|
output SD_MOSI,
|
|
input SD_MISO,
|
|
output SD_CS,
|
|
input SD_CD,
|
|
|
|
//High latency DDR3 RAM interface
|
|
//Use for non-critical time purposes
|
|
output DDRAM_CLK,
|
|
input DDRAM_BUSY,
|
|
output [7:0] DDRAM_BURSTCNT,
|
|
output [28:0] DDRAM_ADDR,
|
|
input [63:0] DDRAM_DOUT,
|
|
input DDRAM_DOUT_READY,
|
|
output DDRAM_RD,
|
|
output [63:0] DDRAM_DIN,
|
|
output [7:0] DDRAM_BE,
|
|
output DDRAM_WE,
|
|
|
|
//SDRAM interface with lower latency
|
|
output SDRAM_CLK,
|
|
output SDRAM_CKE,
|
|
output [12:0] SDRAM_A,
|
|
output [1:0] SDRAM_BA,
|
|
inout [15:0] SDRAM_DQ,
|
|
output SDRAM_DQML,
|
|
output SDRAM_DQMH,
|
|
output SDRAM_nCS,
|
|
output SDRAM_nCAS,
|
|
output SDRAM_nRAS,
|
|
output SDRAM_nWE,
|
|
|
|
`ifdef MISTER_DUAL_SDRAM
|
|
//Secondary SDRAM
|
|
//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
|
|
input SDRAM2_EN,
|
|
output SDRAM2_CLK,
|
|
output [12:0] SDRAM2_A,
|
|
output [1:0] SDRAM2_BA,
|
|
inout [15:0] SDRAM2_DQ,
|
|
output SDRAM2_nCS,
|
|
output SDRAM2_nCAS,
|
|
output SDRAM2_nRAS,
|
|
output SDRAM2_nWE,
|
|
`endif
|
|
|
|
input UART_CTS,
|
|
output UART_RTS,
|
|
input UART_RXD,
|
|
output UART_TXD,
|
|
output UART_DTR,
|
|
input UART_DSR,
|
|
|
|
// Open-drain User port.
|
|
// 0 - D+/RX
|
|
// 1 - D-/TX
|
|
// 2..6 - USR2..USR6
|
|
// Set USER_OUT to 1 to read from USER_IN.
|
|
input [6:0] USER_IN,
|
|
output [6:0] USER_OUT,
|
|
|
|
input OSD_STATUS
|
|
);
|
|
|
|
assign VGA_F1 = 0;
|
|
assign VGA_SCALER= 0;
|
|
assign VGA_DISABLE = 0;
|
|
assign HDMI_FREEZE = 0;
|
|
assign HDMI_BLACKOUT = 0;
|
|
assign HDMI_BOB_DEINT = 0;
|
|
|
|
assign AUDIO_MIX=0;
|
|
|
|
assign USER_OUT = '1;
|
|
assign LED_USER = ioctl_download;
|
|
assign LED_DISK = 0;
|
|
assign LED_POWER = 0;
|
|
assign BUTTONS = 0;
|
|
|
|
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
|
|
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
|
|
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
|
|
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
|
|
|
|
|
|
wire [1:0] ar = status[2:1];
|
|
|
|
assign VIDEO_ARX = (!ar) ? ( 12'd2570) : (ar - 1'd1);
|
|
assign VIDEO_ARY = (!ar) ? ( 12'd2191) : 12'd0;
|
|
|
|
`include "build_id.v"
|
|
localparam CONF_STR = {
|
|
"A.SolmnsKey;;",
|
|
"H0O12,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
|
|
"O35,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
|
|
"-;",
|
|
"O89,Difficulty,Normal,Middle,Easy,Hard;",
|
|
"OAB,Lives,3,5,4,2;",
|
|
"OCD,Timer Speed,Normal,Faster,Slow,Fastest;",
|
|
"OE,Extra,Normal,Difficult;",
|
|
"OGI,Bonus Life,30k 200k 500k,30k,30k 200k,200k,100k 300k 800k,100k,100k 300k,None;",
|
|
"-;",
|
|
//"O7,Cabinet,Cocktail,Upright;",
|
|
"OF,Demo Sound,On,Off;",
|
|
"-;",
|
|
"OOS,Analog Video H-Pos,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31;",
|
|
"OTV,Analog Video V-Pos,0,1,2,3,4,5,6,7;",
|
|
"-;",
|
|
"R0,Reset;",
|
|
"J1,Trig1,Trig2,Start 1P,Start 2P,Coin;",
|
|
"jn,A,B,Start,Select,R;",
|
|
"V,v",`BUILD_DATE
|
|
};
|
|
|
|
wire dsDSND = status[15];
|
|
wire dsCABI = 1'b1; /*status[7]*/ // (upright only)
|
|
wire [1:0] dsLIFE = status[11:10];
|
|
wire [1:0] dsDIFC = status[9:8];
|
|
wire [1:0] dsTSPD = status[13:12];
|
|
wire dsEXTR = status[14];
|
|
wire [2:0] dsBLIF = status[18:16];
|
|
|
|
wire bCabinet = ~dsCABI;
|
|
|
|
wire [7:0] DSW0 = {2'b00,2'b00,dsLIFE,dsCABI,dsDSND};
|
|
wire [7:0] DSW1 = {dsBLIF,dsEXTR,dsTSPD,dsDIFC};
|
|
|
|
|
|
wire [4:0] HOFFS = status[28:24];
|
|
wire [2:0] VOFFS = status[31:29];
|
|
|
|
|
|
//////////////////// CLOCKS ///////////////////
|
|
|
|
wire clk_48M;
|
|
wire clk_hdmi = clk_48M;
|
|
wire clk_sys = clk_48M;
|
|
|
|
pll pll
|
|
(
|
|
.rst(0),
|
|
.refclk(CLK_50M),
|
|
.outclk_0(clk_48M)
|
|
);
|
|
|
|
///////////////////////////////////////////////////
|
|
|
|
wire [31:0] status;
|
|
wire [1:0] buttons;
|
|
wire forced_scandoubler;
|
|
wire direct_video;
|
|
|
|
wire ioctl_download;
|
|
wire ioctl_wr;
|
|
wire [24:0] ioctl_addr;
|
|
wire [7:0] ioctl_dout;
|
|
|
|
wire [15:0] joystk1, joystk2;
|
|
|
|
wire [21:0] gamma_bus;
|
|
|
|
hps_io #(.CONF_STR(CONF_STR)) hps_io
|
|
(
|
|
.clk_sys(clk_sys),
|
|
.HPS_BUS(HPS_BUS),
|
|
|
|
.buttons(buttons),
|
|
|
|
.status(status),
|
|
.status_menumask({15'h0,direct_video}),
|
|
|
|
.forced_scandoubler(forced_scandoubler),
|
|
.gamma_bus(gamma_bus),
|
|
.direct_video(direct_video),
|
|
|
|
.ioctl_download(ioctl_download),
|
|
.ioctl_wr(ioctl_wr),
|
|
.ioctl_addr(ioctl_addr),
|
|
.ioctl_dout(ioctl_dout),
|
|
|
|
.joystick_0(joystk1),
|
|
.joystick_1(joystk2)
|
|
);
|
|
|
|
wire m_up2 = joystk2[3];
|
|
wire m_down2 = joystk2[2];
|
|
wire m_left2 = joystk2[1];
|
|
wire m_right2 = joystk2[0];
|
|
wire m_trig21 = joystk2[4];
|
|
wire m_trig22 = joystk2[5];
|
|
|
|
wire m_start1 = joystk1[6] | joystk2[6];
|
|
wire m_start2 = joystk1[7] | joystk2[7];
|
|
|
|
wire m_up1 = joystk1[3] | (bCabinet ? 1'b0 : m_up2);
|
|
wire m_down1 = joystk1[2] | (bCabinet ? 1'b0 : m_down2);
|
|
wire m_left1 = joystk1[1] | (bCabinet ? 1'b0 : m_left2);
|
|
wire m_right1 = joystk1[0] | (bCabinet ? 1'b0 : m_right2);
|
|
wire m_trig11 = joystk1[4] | (bCabinet ? 1'b0 : m_trig21);
|
|
wire m_trig12 = joystk1[5] | (bCabinet ? 1'b0 : m_trig22);
|
|
|
|
wire m_coin1 = joystk1[8];
|
|
wire m_coin2 = joystk2[8];
|
|
|
|
|
|
///////////////////////////////////////////////////
|
|
|
|
wire hblank, vblank;
|
|
wire ce_vid;
|
|
wire hs, vs;
|
|
wire [3:0] r,g,b;
|
|
|
|
reg ce_pix;
|
|
always @(posedge clk_hdmi) begin
|
|
reg old_clk;
|
|
old_clk <= ce_vid;
|
|
ce_pix <= old_clk & ~ce_vid;
|
|
end
|
|
|
|
arcade_video #(256,12) arcade_video
|
|
(
|
|
.*,
|
|
|
|
.clk_video(clk_hdmi),
|
|
|
|
.RGB_in({r,g,b}),
|
|
.HBlank(hblank),
|
|
.VBlank(vblank),
|
|
.HSync(~hs),
|
|
.VSync(~vs),
|
|
|
|
.fx(status[5:3])
|
|
);
|
|
|
|
wire PCLK;
|
|
wire [8:0] HPOS,VPOS;
|
|
wire [11:0] POUT;
|
|
HVGEN hvgen
|
|
(
|
|
.HPOS(HPOS),.VPOS(VPOS),.PCLK(PCLK),.iRGB(POUT),
|
|
.oRGB({b,g,r}),.HBLK(hblank),.VBLK(vblank),.HSYN(hs),.VSYN(vs),
|
|
.HOFFS(HOFFS),.VOFFS(VOFFS)
|
|
);
|
|
assign ce_vid = PCLK;
|
|
|
|
|
|
wire [15:0] AOUT;
|
|
assign AUDIO_L = AOUT;
|
|
assign AUDIO_R = AUDIO_L;
|
|
assign AUDIO_S = 0; // unsigned PCM
|
|
|
|
|
|
///////////////////////////////////////////////////
|
|
|
|
wire iRST = RESET | status[0] | buttons[1] | ioctl_download;
|
|
|
|
wire [7:0] INP0 = { 2'b11, m_trig11, m_trig12, m_down1, m_up1, m_left1, m_right1 };
|
|
wire [7:0] INP1 = { 2'b11, m_trig21, m_trig22, m_down2, m_up2, m_left2, m_right2 };
|
|
wire [7:0] INP2 = { 5'b11111, (m_coin1|m_coin2), m_start2, m_start1 };
|
|
|
|
FPGA_SOLOMON GameCore (
|
|
.MCLK(clk_48M),.RESET(iRST),
|
|
|
|
.INP0(~INP0),.INP1(~INP1),.INP2(~INP2),
|
|
.DSW0(DSW0),.DSW1(DSW1),
|
|
|
|
.PH(HPOS),.PV(VPOS),.PCLK(PCLK),.POUT(POUT),
|
|
.SND(AOUT),
|
|
|
|
.ROMCL(clk_sys),.ROMAD(ioctl_addr),.ROMDT(ioctl_dout),.ROMEN(ioctl_wr)
|
|
);
|
|
|
|
endmodule
|
|
|
|
|
|
module HVGEN
|
|
(
|
|
output [8:0] HPOS,
|
|
output [8:0] VPOS,
|
|
input PCLK,
|
|
input [11:0] iRGB,
|
|
|
|
output reg [11:0] oRGB,
|
|
output reg HBLK = 1,
|
|
output reg VBLK = 1,
|
|
output reg HSYN = 1,
|
|
output reg VSYN = 1,
|
|
|
|
input [8:0] HOFFS,
|
|
input [8:0] VOFFS
|
|
);
|
|
|
|
reg [8:0] hcnt = 0;
|
|
reg [8:0] vcnt = 0;
|
|
|
|
assign HPOS = hcnt-9'd16;
|
|
assign VPOS = vcnt;
|
|
|
|
wire [8:0] HS_B = 288+(HOFFS*2);
|
|
wire [8:0] HS_E = 32+(HS_B);
|
|
wire [8:0] HS_N = 447+(HS_E-320);
|
|
|
|
wire [8:0] VS_B = 226+(VOFFS*4);
|
|
wire [8:0] VS_E = 4+(VS_B);
|
|
wire [8:0] VS_N = 483+(VS_E-230);
|
|
|
|
always @(posedge PCLK) begin
|
|
case (hcnt)
|
|
15: begin HBLK <= 0; hcnt <= hcnt+9'd1; end
|
|
272: begin HBLK <= 1; hcnt <= hcnt+9'd1; end
|
|
511: begin hcnt <= 0;
|
|
case (vcnt)
|
|
223: begin VBLK <= 1; vcnt <= vcnt+9'd1; end
|
|
511: begin VBLK <= 0; vcnt <= 0; end
|
|
default: vcnt <= vcnt+9'd1;
|
|
endcase
|
|
end
|
|
default: hcnt <= hcnt+9'd1;
|
|
endcase
|
|
|
|
if (hcnt==HS_B) begin HSYN <= 0; end
|
|
if (hcnt==HS_E) begin HSYN <= 1; hcnt <= HS_N; end
|
|
|
|
if (vcnt==VS_B) begin VSYN <= 0; end
|
|
if (vcnt==VS_E) begin VSYN <= 1; vcnt <= VS_N; end
|
|
|
|
oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
|
|
end
|
|
|
|
endmodule
|