mirror of
https://github.com/MiSTer-devel/Arcade-RallyX_MiSTer.git
synced 2026-04-19 03:03:09 +00:00
336 lines
7.7 KiB
Systemverilog
336 lines
7.7 KiB
Systemverilog
// Arcade: New Rally-X
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//
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// Original implimentation and port to MiSTer by MiSTer-X 2019
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [45:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output VGA_CLK,
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//Multiple resolutions are supported using different VGA_CE rates.
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//Must be based on CLK_VIDEO
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output VGA_CE,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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//Base video clock. Usually equals to CLK_SYS.
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output HDMI_CLK,
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//Multiple resolutions are supported using different HDMI_CE rates.
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//Must be based on CLK_VIDEO
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output HDMI_CE,
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output [7:0] HDMI_R,
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output [7:0] HDMI_G,
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output [7:0] HDMI_B,
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output HDMI_HS,
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output HDMI_VS,
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output HDMI_DE, // = ~(VBlank | HBlank)
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output [1:0] HDMI_SL, // scanlines fx
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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output [7:0] HDMI_ARX,
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output [7:0] HDMI_ARY,
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT
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);
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assign VGA_F1 = 0;
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assign USER_OUT = '1;
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assign LED_USER = ioctl_download;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign HDMI_ARX = status[1] ? 8'd16 : 8'd4;
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assign HDMI_ARY = status[1] ? 8'd9 : 8'd3;
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`include "build_id.v"
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localparam CONF_STR = {
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"A.NRALLYX;;",
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"O1,Aspect Ratio,Original,Wide;",
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"-;",
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//"OE,Cabinet,Upright,Cocktail;",
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"O8A,Difficulty,M1,M2,M3,M4,M5,M6,M7,M8;",
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"OBC,Bonus Life,M1,M2,M3,Nothing;",
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"OF,Service Mode,Off,On;",
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"-;",
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"R0,Reset;",
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"J1,Smoke,Start 1P,Start 2P,Coin;",
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"V,v",`BUILD_DATE
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};
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//////////////////// CLOCKS ///////////////////
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wire clk_hdmi;
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wire clk_24M;
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wire clk_sys = clk_24M;
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pll pll
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(
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.rst(0),
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.refclk(CLK_50M),
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.outclk_0(clk_hdmi),
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.outclk_1(clk_24M)
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);
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///////////////////////////////////////////////////
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wire [31:0] status;
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wire [1:0] buttons;
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wire forced_scandoubler;
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wire [21:0] gamma_bus;
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wire ioctl_download;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_dout;
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wire [10:0] ps2_key;
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wire [15:0] joystk1, joystk2;
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hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.conf_str(CONF_STR),
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.buttons(buttons),
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.status(status),
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.forced_scandoubler(forced_scandoubler),
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.gamma_bus(gamma_bus),
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.ioctl_download(ioctl_download),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.joystick_0(joystk1),
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.joystick_1(joystk2),
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.ps2_key(ps2_key)
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);
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wire pressed = ps2_key[9];
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wire [8:0] code = ps2_key[8:0];
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always @(posedge clk_sys) begin
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reg old_state;
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old_state <= ps2_key[10];
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if(old_state != ps2_key[10]) begin
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casex(code)
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'hX75: btn_up <= pressed; // up
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'hX72: btn_down <= pressed; // down
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'hX6B: btn_left <= pressed; // left
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'hX74: btn_right <= pressed; // right
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'h029: btn_fire <= pressed; // space
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'h014: btn_fire <= pressed; // ctrl
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'h005: btn_one_player <= pressed; // F1
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'h006: btn_two_players <= pressed; // F2
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// JPAC/IPAC/MAME Style Codes
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'h016: btn_start_1 <= pressed; // 1
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'h01E: btn_start_2 <= pressed; // 2
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'h02E: btn_coin_1 <= pressed; // 5
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'h036: btn_coin_2 <= pressed; // 6
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'h02D: btn_up_2 <= pressed; // R
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'h02B: btn_down_2 <= pressed; // F
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'h023: btn_left_2 <= pressed; // D
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'h034: btn_right_2 <= pressed; // G
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'h01C: btn_fire_2 <= pressed; // A
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'h01B: btn_fire_2 <= pressed; // S
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endcase
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end
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end
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reg btn_up = 0;
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reg btn_down = 0;
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reg btn_right = 0;
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reg btn_left = 0;
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reg btn_fire = 0;
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reg btn_one_player = 0;
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reg btn_two_players = 0;
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reg btn_start_1 = 0;
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reg btn_start_2 = 0;
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reg btn_coin_1 = 0;
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reg btn_coin_2 = 0;
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reg btn_up_2 = 0;
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reg btn_down_2 = 0;
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reg btn_left_2 = 0;
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reg btn_right_2 = 0;
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reg btn_fire_2 = 0;
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wire bCabinet = 1'b0; // (upright only)
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wire m_up2 = btn_up_2 | joystk2[3];
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wire m_down2 = btn_down_2 | joystk2[2];
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wire m_left2 = btn_left_2 | joystk2[1];
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wire m_right2 = btn_right_2 | joystk2[0];
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wire m_trig2 = btn_fire_2 | joystk2[4];
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wire m_start1 = btn_one_player | joystk1[5] | joystk2[5] | btn_start_1;
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wire m_start2 = btn_two_players | joystk1[6] | joystk2[6] | btn_start_2;
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wire m_up1 = btn_up | joystk1[3] | (bCabinet ? 1'b0 : m_up2);
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wire m_down1 = btn_down | joystk1[2] | (bCabinet ? 1'b0 : m_down2);
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wire m_left1 = btn_left | joystk1[1] | (bCabinet ? 1'b0 : m_left2);
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wire m_right1 = btn_right | joystk1[0] | (bCabinet ? 1'b0 : m_right2);
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wire m_trig1 = btn_fire | joystk1[4] | (bCabinet ? 1'b0 : m_trig2);
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wire m_coin1 = btn_one_player | btn_coin_1 | joystk1[7];
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wire m_coin2 = btn_two_players| btn_coin_2 | joystk2[7];
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///////////////////////////////////////////////////
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wire hblank, vblank;
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wire ce_vid;
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wire hs, vs;
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wire [3:0] r,g,b;
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reg ce_pix;
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always @(posedge clk_hdmi) begin
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reg old_clk;
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old_clk <= ce_vid;
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ce_pix <= old_clk & ~ce_vid;
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end
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arcade_rotate_fx #(288,224,12) arcade_video
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(
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.*,
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.clk_video(clk_hdmi),
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.RGB_in({r,g,b}),
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.HBlank(hblank),
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.VBlank(vblank),
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.HSync(~hs),
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.VSync(~vs),
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.fx(0),
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.no_rotate(1'b1)
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);
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wire PCLK;
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wire [8:0] HPOS,VPOS;
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wire [11:0] POUT;
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HVGEN hvgen
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(
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.HPOS(HPOS),.VPOS(VPOS),.PCLK(PCLK),.iRGB(POUT),
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.oRGB({b,g,r}),.HBLK(hblank),.VBLK(vblank),.HSYN(hs),.VSYN(vs)
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);
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assign ce_vid = PCLK;
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wire [15:0] AOUT;
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assign AUDIO_L = AOUT;
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assign AUDIO_R = AUDIO_L;
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assign AUDIO_S = 0; // unsigned PCM
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///////////////////////////////////////////////////
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wire iRST = RESET | status[0] | buttons[1] | ioctl_download;
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wire [7:0] iDSW = ~{ 2'b00, status[10:8], status[12:11], status[15] };
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wire [7:0] iCTR1 = ~{ m_coin1, m_start1, m_up1, m_down1, m_right1, m_left1, m_trig1, 1'b0 };
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wire [7:0] iCTR2 = ~{ m_coin2, m_start2, m_up2, m_down2, m_right2, m_left2, m_trig2, bCabinet };
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wire [7:0] oPIX;
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wire [7:0] oSND;
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fpga_NRX GameCore (
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.RESET(iRST),.CLK24M(clk_24M),
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.HP(HPOS),.VP(VPOS),.PCLK(PCLK),
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.POUT(oPIX),.SND(oSND),
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.DSW(iDSW),.CTR1(iCTR1),.CTR2(iCTR2),
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.ROMCL(clk_sys),.ROMAD(ioctl_addr),.ROMDT(ioctl_dout),.ROMEN(ioctl_wr)
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);
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assign POUT = {oPIX[7:6],2'b00,oPIX[5:3],1'b0,oPIX[2:0],1'b0};
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assign AOUT = {oSND,8'h0};
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endmodule
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module HVGEN
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(
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output [8:0] HPOS,
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output [8:0] VPOS,
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input PCLK,
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input [11:0] iRGB,
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output reg [11:0] oRGB,
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output reg HBLK = 1,
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output reg VBLK = 1,
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output reg HSYN = 1,
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output reg VSYN = 1
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);
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reg [8:0] hcnt = 0;
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reg [8:0] vcnt = 0;
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assign HPOS = hcnt;
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assign VPOS = vcnt;
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always @(posedge PCLK) begin
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case (hcnt)
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288: begin HBLK <= 1; hcnt <= hcnt+1; end
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311: begin HSYN <= 0; hcnt <= hcnt+1; end
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342: begin HSYN <= 1; hcnt <= 471; end
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511: begin HBLK <= 0; hcnt <= 0;
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case (vcnt)
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223: begin VBLK <= 1; vcnt <= vcnt+1; end
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226: begin VSYN <= 0; vcnt <= vcnt+1; end
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233: begin VSYN <= 1; vcnt <= 483; end
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511: begin VBLK <= 0; vcnt <= 0; end
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default: vcnt <= vcnt+1;
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endcase
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end
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default: hcnt <= hcnt+1;
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endcase
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oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
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end
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endmodule
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