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https://github.com/MiSTer-devel/Arcade-RallyX_MiSTer.git
synced 2026-04-19 03:03:09 +00:00
112 lines
1.7 KiB
Verilog
112 lines
1.7 KiB
Verilog
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module LINEBUF1024_9
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(
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input CL0,
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input [9:0] AD0,
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input WE0,
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output [8:0] DO0,
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input CL1,
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input [9:0] AD1,
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input WE1,
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input [8:0] DI1
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);
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LINEBUF lbcore (
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.clock_a(CL0),
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.address_a(AD0),
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.data_a(9'h0),
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.wren_a(WE0),
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.q_a(DO0),
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.clock_b(CL1),
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.address_b(AD1),
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.data_b(DI1),
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.wren_b(WE1)
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);
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endmodule
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module GSPRAM #(parameter AW,parameter DW)
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(
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input CL,
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input [(AW-1):0] AD,
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input WE,
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input [(DW-1):0] DI,
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output reg [(DW-1):0] DO
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);
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reg [(DW-1):0] core[0:((2**AW)-1)];
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always @(posedge CL) begin
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DO <= core[AD];
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if (WE) core[AD] <= DI;
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end
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endmodule
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module GDPRAM #(parameter AW,parameter DW)
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(
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input CL0,
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input [(AW-1):0] AD0,
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output reg [(DW-1):0] DO0,
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input CL1,
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input [(AW-1):0] AD1,
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input WE1,
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input [(DW-1):0] DI1,
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output reg [(DW-1):0] DO1
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);
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reg [(DW-1):0] core[0:((2**AW)-1)];
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always @(posedge CL0) DO0 <= core[AD0];
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always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end
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endmodule
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module GLINEBUF #(parameter AW,parameter DW)
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(
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input CL0,
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input [(AW-1):0] AD0,
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input WE0,
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output reg [(DW-1):0] DO0,
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input CL1,
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input [(AW-1):0] AD1,
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input WE1,
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input [(DW-1):0] DI1
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);
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reg [(DW-1):0] core[0:((2**AW)-1)];
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always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end
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always @(posedge CL1) if (WE1) core[AD1] <= DI1;
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endmodule
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module DLROM #(parameter AW,parameter DW)
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(
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input CL0,
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input [(AW-1):0] AD0,
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output reg [(DW-1):0] DO0,
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input CL1,
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input [(AW-1):0] AD1,
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input [(DW-1):0] DI1,
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input WE1
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);
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reg [(DW-1):0] core[0:((2**AW)-1)];
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always @(posedge CL0) DO0 <= core[AD0];
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always @(posedge CL1) if (WE1) core[AD1] <= DI1;
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endmodule
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