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https://github.com/MiSTer-devel/Arcade-RallyX_MiSTer.git
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247 lines
10 KiB
Verilog
247 lines
10 KiB
Verilog
// megafunction wizard: %RAM: 2-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: LINEBUF.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2017 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module LINEBUF (
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address_a,
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address_b,
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clock_a,
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clock_b,
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data_a,
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data_b,
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wren_a,
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wren_b,
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q_a,
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q_b);
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input [9:0] address_a;
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input [9:0] address_b;
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input clock_a;
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input clock_b;
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input [8:0] data_a;
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input [8:0] data_b;
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input wren_a;
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input wren_b;
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output [8:0] q_a;
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output [8:0] q_b;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock_a;
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tri0 wren_a;
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tri0 wren_b;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [8:0] sub_wire0;
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wire [8:0] sub_wire1;
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wire [8:0] q_a = sub_wire0[8:0];
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wire [8:0] q_b = sub_wire1[8:0];
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altsyncram altsyncram_component (
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.address_a (address_a),
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.address_b (address_b),
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.clock0 (clock_a),
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.clock1 (clock_b),
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.data_a (data_a),
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.data_b (data_b),
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.wren_a (wren_a),
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.wren_b (wren_b),
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.q_a (sub_wire0),
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.q_b (sub_wire1),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.eccstatus (),
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.rden_a (1'b1),
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.rden_b (1'b1));
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defparam
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altsyncram_component.address_reg_b = "CLOCK1",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.indata_reg_b = "CLOCK1",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 1024,
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altsyncram_component.numwords_b = 1024,
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altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_a = "UNREGISTERED",
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altsyncram_component.outdata_reg_b = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.ram_block_type = "M10K",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.widthad_a = 10,
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altsyncram_component.widthad_b = 10,
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altsyncram_component.width_a = 9,
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altsyncram_component.width_b = 9,
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altsyncram_component.width_byteena_a = 1,
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altsyncram_component.width_byteena_b = 1,
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altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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// Retrieval info: PRIVATE: CLRq NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "5"
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// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MEMSIZE NUMERIC "9216"
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// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING ""
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// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
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// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
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// Retrieval info: PRIVATE: REGdata NUMERIC "1"
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// Retrieval info: PRIVATE: REGq NUMERIC "0"
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// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
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// Retrieval info: PRIVATE: REGrren NUMERIC "0"
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// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGwren NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
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// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
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// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
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// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
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// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
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// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
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// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
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// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
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// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: enable NUMERIC "0"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
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// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
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// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
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// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
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// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
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// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
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// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
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// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
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// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
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// Retrieval info: USED_PORT: data_a 0 0 9 0 INPUT NODEFVAL "data_a[8..0]"
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// Retrieval info: USED_PORT: data_b 0 0 9 0 INPUT NODEFVAL "data_b[8..0]"
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// Retrieval info: USED_PORT: q_a 0 0 9 0 OUTPUT NODEFVAL "q_a[8..0]"
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// Retrieval info: USED_PORT: q_b 0 0 9 0 OUTPUT NODEFVAL "q_b[8..0]"
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// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
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// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
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// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
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// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
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// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
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// Retrieval info: CONNECT: @data_a 0 0 9 0 data_a 0 0 9 0
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// Retrieval info: CONNECT: @data_b 0 0 9 0 data_b 0 0 9 0
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// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
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// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
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// Retrieval info: CONNECT: q_a 0 0 9 0 @q_a 0 0 9 0
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// Retrieval info: CONNECT: q_b 0 0 9 0 @q_b 0 0 9 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF_bb.v TRUE
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// Retrieval info: LIB_FILE: altera_mf
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