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43 lines
1.5 KiB
Verilog
43 lines
1.5 KiB
Verilog
/*
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MIT License
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Copyright (c) 2019 Richard Eng
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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*/
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/*
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Pong - Horizontal Sync Circuit
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------------------------------
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*/
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`default_nettype none
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module hsync
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(
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input wire mclk, _hreset, h16, h32, h64,
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output wire hblank, _hblank, _hsync
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);
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// hack-hack: "and" with clock to simulate propagation delay of ripple counter...
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srlatch h5bc(~mclk, ~(h16 & h64), _hreset, _hblank, hblank);
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assign _hsync = ~(hblank & h32);
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endmodule
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