mirror of
https://github.com/MiSTer-devel/Arcade-PolyPlay_MiSTer.git
synced 2026-04-26 03:02:37 +00:00
1400ede7c6
DIVIDER100hz wasn't assigning the default value as intended because it wasn't declared as a constant, fixed that.
105 lines
3.2 KiB
VHDL
105 lines
3.2 KiB
VHDL
--
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-- reworked for PolyPlay by Niels Lueddecke in 2021
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--
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-- Copyright (c) 2015, $ME
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-- All rights reserved.
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--
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-- Redistribution and use in source and synthezised forms, with or without modification, are permitted
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-- provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice, this list of conditions
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-- and the following disclaimer.
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--
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-- 2. Redistributions in synthezised form must reproduce the above copyright notice, this list of conditions
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-- and the following disclaimer in the documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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-- WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- Erzeugung der Takte fuer KC
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-- CPU+CTC
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity sysclock is
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port (
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clk : in std_logic;
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cpuClkEn : out std_logic; -- 2,4576 MHz
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ctcClk : out std_logic; -- cpuClkEn / 4
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nmi100hz : out std_logic -- 100hz from power supply
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);
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end sysclock;
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architecture rtl of sysclock is
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constant c_DIVIDER : unsigned(7 downto 0) := x"14"; -- 20
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constant c_FRACT_DIVIER : unsigned(7 downto 0) := x"03"; -- 3
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constant DIVIDER100hz : unsigned(19 downto 0) := x"7a11f"; -- 499999
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signal DIVIDER : unsigned(7 downto 0);
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signal FRACT_DIVIER : unsigned(7 downto 0);
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signal divide100 : unsigned(19 downto 0) := (others => '0');
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signal mainDivider : unsigned(7 downto 0) := (others => '0');
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signal fractDivider : unsigned(7 downto 0) := (others => '0');
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signal mainClkEn : std_logic;
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signal ctcClk_cnt : unsigned(3 downto 0) := (others => '0');
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begin
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cpuClkEn <= mainClkEn;
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-- Ziel: 2,4576 MHz
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-- genauer Teiler: 20,34505
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-- 50 MHz durch 20,333333 dividieren
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-- --> 2,459 MHz
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process(clk)
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begin
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if rising_edge(clk) then
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-- turbo setting
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DIVIDER <= c_DIVIDER;
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FRACT_DIVIER <= c_FRACT_DIVIER;
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-- for cpu, multiplied by turbo
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if (mainDivider > 0) then
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mainDivider <= mainDivider - 1;
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mainClkEn <= '0';
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else
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if (fractDivider>0) then
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mainDivider <= DIVIDER - 1;
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fractDivider <= fractDivider - 1;
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else
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mainDivider <= DIVIDER;
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fractDivider <= FRACT_DIVIER-1;
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end if;
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mainClkEn <= '1';
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ctcClk <= ctcClk_cnt(1);
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ctcClk_cnt <= ctcClk_cnt + 1;
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end if;
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-- 100hz
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nmi100hz <= '1';
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if divide100 > 0 then
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divide100 <= divide100 - 1;
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if divide100 < 10000 then
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nmi100hz <= '0';
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end if;
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else
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divide100 <= DIVIDER100hz;
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end if;
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end if;
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end process;
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end rtl; |