mirror of
https://github.com/MiSTer-devel/Arcade-KickAndRun_MiSTer.git
synced 2026-05-17 03:02:24 +00:00
457 lines
12 KiB
Verilog
457 lines
12 KiB
Verilog
`include "clocks.svh"
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module core(
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input reset,
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input clk_sys,
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input [7:0] dsw1,
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input [7:0] dsw2,
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input [7:0] in0,
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input [7:0] in1,
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input [7:0] in2,
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input [7:0] in3,
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input [7:0] in4,
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input [7:0] in5,
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input [7:0] in6,
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input [7:0] in7,
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output [3:0] red,
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output [3:0] green,
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output [3:0] blue,
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output hb,
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output vb,
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output hs,
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output vs,
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output ce_pix,
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input ioctl_download,
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input [26:0] ioctl_addr,
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input [15:0] ioctl_dout,
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input ioctl_wr,
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output [15:0] sound_mix
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);
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wire [15:0] mcpu_ab;
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wire [7:0] mcpu_din;
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wire [7:0] mcpu_dout;
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wire mcpu_rd;
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wire mcpu_wr;
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wire mcpu_io;
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wire mcpu_m1;
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reg mcpu_wait;
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wire mcpu_rom1_en;
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wire mcpu_rom2_en;
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wire mcpu_scrn_en;
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wire mcpu_ps4r_en;
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wire mcpu_reg1_wr;
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wire mcpu_reg2_wr;
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wire mcpu_in3_rd;
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wire mcpu_tmcl_en;
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wire mcpu_exit_en;
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wire scpu_rom_en;
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wire scpu_wrk_en;
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wire scpu_ram_en;
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wire scpu_snd_en;
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wire ecpu_rom_en;
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wire ecpu_ram_en;
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wire ecpu_ext_en;
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wire ecpu_pt0_en;
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wire ecpu_pt1_en;
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wire ecpu_pt2_en;
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wire ecpu_pt3_en;
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wire ecpu_pt4_wr;
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wire ecpu_tmc_en;
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wire [7:0] scpu_din;
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wire [7:0] scpu_dout;
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wire [15:0] scpu_ab;
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wire scpu_rd;
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wire scpu_wr;
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wire scpu_mreq;
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wire scpu_io;
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reg scpu_wait;
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wire [7:0] mcpu_rom_data;
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wire [7:0] exit_dout_a;
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wire [7:0] exit_dout_b;
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wire [7:0] ps4_dout_a;
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wire [7:0] ps4_dout_b;
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wire [7:0] scr_dout_a;
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wire [7:0] scr_dout_b;
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wire [7:0] scpu_ram_dout;
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wire [16:0] char_rom_addr;
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wire [7:0] char_data1;
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wire [7:0] char_data2;
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wire [7:0] pal_rom_addr;
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wire [3:0] pal_rom_data1;
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wire [3:0] pal_rom_data2;
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wire [3:0] pal_rom_data3;
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wire [12:0] sco_addr;
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wire exit_wren_a = mcpu_exit_en & mcpu_wr;
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wire exit_wren_b = ecpu_ext_en & ecpu_wr;
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wire ps4_wren_a = mcpu_ps4r_en & mcpu_wr;
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wire [7:0] mcu_p1 = in0;
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wire [4:0] mcu_p2;
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wire [7:0] mcu_p3_i;
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wire [7:0] mcu_p3_o;
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wire [7:0] mcu_p4;
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wire mcu_ps4_en;
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wire mcu_jh_en;
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wire mcu_jl_en;
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wire [11:0] mcu_ab = { mcu_p2[0], 3'b0, mcu_p4 };
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wire [7:0] scpu_rom_data;
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wire [7:0] ecpu_din;
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wire [7:0] ecpu_dout;
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wire [15:0] ecpu_ab;
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wire ecpu_rd;
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wire ecpu_wr;
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wire ecpu_mreq;
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wire ecpu_io;
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wire [7:0] ecpu_rom_data;
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wire [7:0] ecpu_ram_dout;
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wire [2:0] bank_num = mcpu_reg1[2:0]; // bit 2 is ROM1/0 switch, pin14 is connected to the bank register through PAL16G
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reg [7:0] mcpu_reg1;
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reg [7:0] mcpu_reg2;
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wire [7:0] ym_dout;
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always @(posedge clk_sys) begin
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if (mcpu_wr & mcpu_reg1_wr) mcpu_reg1 <= mcpu_dout; // 15H
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if (mcpu_wr & mcpu_reg2_wr) mcpu_reg2 <= mcpu_dout; // 14H
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end
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assign mcpu_din =
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mcpu_in3_rd ? in3 :
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mcpu_scrn_en ? scr_dout_b :
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mcpu_ps4r_en ? ps4_dout_a :
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mcpu_exit_en ? exit_dout_a :
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mcpu_rom1_en ? mcpu_rom_data :
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mcpu_rom2_en ? mcpu_rom_data : 8'h0;
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assign scpu_din =
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scpu_snd_en ? ym_dout :
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scpu_wrk_en ? scr_dout_a :
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scpu_rom_en ? scpu_rom_data :
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scpu_ram_en ? scpu_ram_dout : 8'h0;
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assign ecpu_din =
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ecpu_pt0_en ? in4 :
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ecpu_pt1_en ? in5 :
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ecpu_pt2_en ? in6 :
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ecpu_pt3_en ? in7 :
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ecpu_ext_en ? exit_dout_b :
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ecpu_ram_en ? ecpu_ram_dout :
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ecpu_rom_en ? ecpu_rom_data : 8'h0;
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assign mcu_p3_i =
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mcu_ps4_en ? ps4_dout_b :
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ps4_rd_prt ? (~mcu_ab[0] ? in2 : in1) :
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8'd0;
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mcpu mcpu(
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.reset ( reset ),
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.clk_sys ( clk_sys ),
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.mcpu_din ( mcpu_din ),
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.mcpu_dout ( mcpu_dout ),
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.mcpu_ab ( mcpu_ab ),
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.mcpu_rd ( mcpu_rd ),
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.mcpu_wr ( mcpu_wr ),
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.mcpu_io ( mcpu_io ),
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.mcpu_m1 ( mcpu_m1 ),
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.mcpu_wait ( mcpu_wait ),
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.sirq_n ( ~vb )
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);
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mcpu_rom u_mcpu_rom(
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.clk_sys ( clk_sys ),
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.mcpu_ab ( mcpu_ab ),
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.bank_num ( bank_num ),
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.mcpu_rom_data ( mcpu_rom_data ),
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.mcpu_rom1_en ( mcpu_rom1_en ),
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.mcpu_rom2_en ( mcpu_rom2_en ),
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.ioctl_download ( ioctl_download ),
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout ),
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.ioctl_wr ( ioctl_wr )
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);
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scpu scpu(
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.reset ( reset | ~mcpu_reg2[2] ),
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.clk_sys ( clk_sys ),
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.scpu_din ( scpu_din ),
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.scpu_dout ( scpu_dout ),
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.scpu_ab ( scpu_ab ),
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.scpu_rd ( scpu_rd ),
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.scpu_wr ( scpu_wr ),
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.scpu_mreq ( scpu_mreq ),
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.scpu_io ( scpu_io ),
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.scpu_wait ( scpu_wait ),
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.irq_n ( ~vb )
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);
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ram #(13,8) scpu_ram(
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.clk ( clk_sys ),
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.addr ( scpu_ab[12:0] ),
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.din ( scpu_dout ),
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.q ( scpu_ram_dout ),
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.rd_n ( 1'b0 ),
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.wr_n ( ~scpu_wr ),
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.ce_n ( ~scpu_ram_en )
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);
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scpu_rom u_scpu_rom(
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.clk_sys ( clk_sys ),
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.scpu_ab ( scpu_ab ),
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.scpu_rom_data ( scpu_rom_data ),
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.ioctl_download ( ioctl_download ),
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout ),
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.ioctl_wr ( ioctl_wr )
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);
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ecpu ecpu(
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.reset ( reset | mcpu_reg2[2] ),
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.clk_sys ( clk_sys ),
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.ecpu_din ( ecpu_din ),
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.ecpu_dout ( ecpu_dout ),
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.ecpu_ab ( ecpu_ab ),
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.ecpu_rd ( ecpu_rd ),
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.ecpu_wr ( ecpu_wr ),
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.ecpu_mreq ( ecpu_mreq ),
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.ecpu_io ( ecpu_io ),
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.vb ( vb )
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);
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ecpu_rom u_ecpu_rom(
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.clk_sys ( clk_sys ),
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.ecpu_ab ( ecpu_ab ),
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.ecpu_rom_data ( ecpu_rom_data ),
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.ioctl_download ( ioctl_download ),
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout ),
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.ioctl_wr ( ioctl_wr )
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);
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addr_decode u_addr_decode(
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.mcpu_ab ( mcpu_ab ),
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.scpu_ab ( scpu_ab ),
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.ecpu_ab ( ecpu_ab ),
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.mcu_ab ( mcu_ab ),
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.ecpu_wr ( ecpu_wr ),
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.ecpu_rd ( ecpu_rd ),
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.mcpu_rom1_en ( mcpu_rom1_en ),
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.mcpu_rom2_en ( mcpu_rom2_en ),
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.mcpu_scrn_en ( mcpu_scrn_en ),
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.mcpu_ps4r_en ( mcpu_ps4r_en ),
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.mcpu_reg1_wr ( mcpu_reg1_wr ),
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.mcpu_reg2_wr ( mcpu_reg2_wr ),
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.mcpu_in3_rd ( mcpu_in3_rd ),
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.mcpu_tmcl_en ( mcpu_tmcl_en ),
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.mcpu_exit_en ( mcpu_exit_en ),
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.scpu_rom_en ( scpu_rom_en ),
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.scpu_wrk_en ( scpu_wrk_en ),
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.scpu_ram_en ( scpu_ram_en ),
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.scpu_snd_en ( scpu_snd_en ),
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.ecpu_rom_en ( ecpu_rom_en ),
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.ecpu_ram_en ( ecpu_ram_en ),
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.ecpu_ext_en ( ecpu_ext_en ),
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.ecpu_pt0_en ( ecpu_pt0_en ),
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.ecpu_pt1_en ( ecpu_pt1_en ),
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.ecpu_pt2_en ( ecpu_pt2_en ),
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.ecpu_pt3_en ( ecpu_pt3_en ),
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.ecpu_pt4_wr ( ecpu_pt4_wr ),
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.ecpu_tmc_en ( ecpu_tmc_en ),
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.mcu_ps4_en ( mcu_ps4_en ),
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.mcu_jh_en ( mcu_jh_en ),
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.mcu_jl_en ( mcu_jl_en )
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);
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mcu u_mcu(
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.reset ( reset | ~mcpu_reg2[1] ),
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.clk_sys ( clk_sys ),
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.mcu_p1 ( mcu_p1 ),
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.mcu_p2 ( mcu_p2 ),
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.mcu_p3_o ( mcu_p3_o ),
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.mcu_p3_i ( mcu_p3_i ),
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.mcu_p4 ( mcu_p4 ),
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.mcu_irq ( ),
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.mcu_nmi ( ),
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.ioctl_download ( ioctl_download ),
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout ),
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.ioctl_wr ( ioctl_wr ),
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.vb ( vb )
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);
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ram #(11,8) ecpu_ram(
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.clk ( clk_sys ),
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.addr ( ecpu_ab[10:0] ),
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.din ( ecpu_dout ),
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.q ( ecpu_ram_dout ),
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.rd_n ( 1'b0 ),
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.wr_n ( ~ecpu_wr ),
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.ce_n ( ~ecpu_ram_en )
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);
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dpram #(11,8) exit(
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.address_a ( mcpu_ab[10:0] ),
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.address_b ( ecpu_ab[10:0] ),
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.clock ( clk_sys ),
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.data_a ( mcpu_dout ),
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.data_b ( ecpu_dout ),
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.rden_a ( 1'b1 ),
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.rden_b ( 1'b1 ),
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.wren_a ( exit_wren_a ),
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.wren_b ( exit_wren_b ),
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.q_a ( exit_dout_a ),
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.q_b ( exit_dout_b )
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);
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wire ps4_wren_b = ~mcu_p2[4] & mcu_p2[0] & ~mcu_p2[2];
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wire ps4_rd_prt = mcu_p2[4] & ~mcu_p2[0] & mcu_p2[2];
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dpram #(11,8) ps4r(
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.address_a ( mcpu_ab[10:0] ),
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.address_b ( mcu_ab[10:0] ),
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.clock ( clk_sys ),
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.data_a ( mcpu_dout ),
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.data_b ( mcu_p3_o ),
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.rden_a ( 1'b1 ),
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.rden_b ( 1'b1 ),
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.wren_a ( ps4_wren_a ),
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.wren_b ( ps4_wren_b ),
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.q_a ( ps4_dout_a ),
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.q_b ( ps4_dout_b )
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);
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reg [13:0] scr_ram_addr_bus;
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reg scr_ram_wr;
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always @* begin
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dma_wait = 1'b0;
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scr_ram_wr = 1'b0;
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if (scpu_wrk_en) begin
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dma_wait = dma_en ? 1'b1 : 1'b0;
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scr_ram_wr = scpu_wr;
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scr_ram_addr_bus = scpu_ab[13:0];
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end
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else if (dma_en) begin
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scr_ram_addr_bus = { 1'b0, dma_addr };
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end
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end
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reg dma_wait;
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wire [12:0] dma_addr;
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wire [7:0] dma_data = scr_dout_a;
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wire dma_en;
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dpram #(14,8) scr1(
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.clock ( clk_sys ),
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.address_a ( scr_ram_addr_bus ), // SCPU | DMA
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.address_b ( mcpu_ab[13:0] ),
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.data_a ( scpu_dout ),
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.data_b ( mcpu_dout ),
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.rden_a ( 1'b1 ),
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.rden_b ( 1'b1 ),
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.wren_a ( scr_ram_wr ),
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.wren_b ( mcpu_scrn_en ? mcpu_wr : 1'b0 ),
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.q_a ( scr_dout_a ),
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.q_b ( scr_dout_b )
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);
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video video(
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.reset ( reset ),
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.clk_sys ( clk_sys ),
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.dma_addr ( dma_addr ),
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.dma_data ( dma_data ),
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.dma_en ( dma_en ),
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.dma_wait ( dma_wait ),
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.bank ( mcpu_reg1[5] ),
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.char_rom_addr ( char_rom_addr ),
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.char_data1 ( char_data1 ),
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.char_data2 ( char_data2 ),
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.pal_rom_addr ( pal_rom_addr ),
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.pal_rom_data1 ( pal_rom_data1 ),
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.pal_rom_data2 ( pal_rom_data2 ),
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.pal_rom_data3 ( pal_rom_data3 ),
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.red ( red ),
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.green ( green ),
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.blue ( blue ),
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.hb ( hb ),
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.vb ( vb ),
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.hs ( hs ),
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.vs ( vs ),
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.ce_pix ( ce_pix )
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);
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data vdata(
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.clk_sys ( clk_sys ),
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.char_rom_addr ( char_rom_addr ),
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.char_data1 ( char_data1 ),
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.char_data2 ( char_data2 ),
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.pal_rom_addr ( pal_rom_addr ),
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.pal_rom_data1 ( pal_rom_data1 ),
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.pal_rom_data2 ( pal_rom_data2 ),
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.pal_rom_data3 ( pal_rom_data3 ),
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.ioctl_download ( ioctl_download ),
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout ),
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.ioctl_wr ( ioctl_wr )
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);
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wire cen_6, clk_6;
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clk_en #(CORE_CLK_6) u_ck_en(clk_sys, cen_6, clk_6);
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wire jt03_wr_n = ~(scpu_snd_en & scpu_wr);
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wire [7:0] jt03_din = ~jt03_wr_n ? scpu_dout : 8'd0;
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reg jt03_addr;
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always @(posedge clk_sys)
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if (scpu_snd_en) jt03_addr <= scpu_ab[0];
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jt03 u_jt03(
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.rst ( reset ),
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.clk ( clk_sys ),
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.cen ( cen_6 ),
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.din ( jt03_din ),
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.addr ( jt03_addr ),
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.cs_n ( ~(scpu_snd_en & scpu_mreq) ),
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.wr_n ( jt03_wr_n ),
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.dout ( ym_dout ),
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.irq_n ( ),
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.IOA_in ( dsw1 ),
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.IOB_in ( dsw2 ),
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.psg_A ( ),
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.psg_B ( ),
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.psg_C ( ),
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.fm_snd ( ),
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.psg_snd ( ),
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.snd ( sound_mix ),
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.snd_sample ( )
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);
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endmodule
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