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88 lines
1.5 KiB
Verilog
88 lines
1.5 KiB
Verilog
/********************************************
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RAM Modules for "FPGA Gaplus"
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Copyright (c) 2007,2019 MiSTer-X
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*********************************************/
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module DPRAM_1024V( CL0, ADRS0, IN0, OUT0, WR0, CL1, ADRS1, OUT1 );
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input CL0;
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input [9:0] ADRS0;
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input [7:0] IN0;
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output [7:0] OUT0;
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input WR0;
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input CL1;
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input [9:0] ADRS1;
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output [7:0] OUT1;
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reg [7:0] ramcore[0:1023];
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reg [7:0] OUT0;
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reg [7:0] OUT1;
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always @( posedge CL0 ) begin
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if ( WR0 ) ramcore[ADRS0] <= IN0;
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else OUT0 <= ramcore[ADRS0];
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end
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always @( posedge CL1 ) begin
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OUT1 <= ramcore[ADRS1];
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end
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endmodule
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module DPRAM_2048( CL0, ADRS0, IN0, OUT0, WR0, CL1, ADRS1, IN1, OUT1, WR1 );
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input CL0;
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input [10:0] ADRS0;
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input [7:0] IN0;
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output [7:0] OUT0;
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input WR0;
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input CL1;
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input [10:0] ADRS1;
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input [7:0] IN1;
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output [7:0] OUT1;
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input WR1;
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reg [7:0] ramcore[0:2047];
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reg [7:0] OUT0;
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reg [7:0] OUT1;
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always @( posedge CL0 ) begin
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if ( WR0 ) ramcore[ADRS0] <= IN0;
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else OUT0 <= ramcore[ADRS0];
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end
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always @( posedge CL1 ) begin
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if ( WR1 ) ramcore[ADRS1] <= IN1;
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else OUT1 <= ramcore[ADRS1];
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end
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endmodule
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module DPRAM_2048V( CL0, ADRS0, IN0, OUT0, WR0, CL1, ADRS1, OUT1 );
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input CL0;
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input [10:0] ADRS0;
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input [7:0] IN0;
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output [7:0] OUT0;
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input WR0;
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input CL1;
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input [10:0] ADRS1;
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output [7:0] OUT1;
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reg [7:0] ramcore[0:2047];
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reg [7:0] OUT0;
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reg [7:0] OUT1;
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always @( posedge CL0 ) begin
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if ( WR0 ) ramcore[ADRS0] <= IN0;
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else OUT0 <= ramcore[ADRS0];
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end
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always @( posedge CL1 ) begin
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OUT1 <= ramcore[ADRS1];
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end
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endmodule
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