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https://github.com/MiSTer-devel/Arcade-Gaplus_MiSTer.git
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66 lines
759 B
Verilog
66 lines
759 B
Verilog
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module busdriver
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(
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input iENABLE,
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input iSELECT,
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input [31:0] iBUS0,
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input [31:0] iBUS1,
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output [31:0] oBUS
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);
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assign oBUS = iENABLE ? ( iSELECT ? iBUS0 : iBUS1 ) : 0;
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endmodule
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module dataselector2
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(
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output [7:0] oDATA,
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input iSEL0,
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input [7:0] iDATA0,
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input iSEL1,
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input [7:0] iDATA1,
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input [7:0] dData
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);
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assign oDATA = iSEL0 ? iDATA0 :
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iSEL1 ? iDATA1 :
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dData;
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endmodule
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module dataselector4
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(
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output [7:0] oDATA,
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input iSEL0,
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input [7:0] iDATA0,
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input iSEL1,
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input [7:0] iDATA1,
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input iSEL2,
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input [7:0] iDATA2,
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input iSEL3,
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input [7:0] iDATA3,
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input [7:0] dData
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);
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assign oDATA = iSEL0 ? iDATA0 :
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iSEL1 ? iDATA1 :
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iSEL2 ? iDATA2 :
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iSEL3 ? iDATA3 :
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dData;
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endmodule
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