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38 lines
806 B
Verilog
38 lines
806 B
Verilog
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module decrypt(
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input [7:0] encryption,
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input [7:0] data_in,
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input [15:0] addr,
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output reg [7:0] data_out
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);
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always @* begin
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case (encryption)
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8'd0: data_out = data_in;
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8'd1: data_out = {
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addr[13] ? (~addr[2] ? ~data_in[0] : data_in[0]) : ~data_in[7],
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data_in[2],
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data_in[5],
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data_in[1],
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data_in[3],
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data_in[6],
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data_in[4],
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addr[13] ? (~addr[2] ? ~data_in[7] : data_in[7]) : ~data_in[0]
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};
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8'd2: data_out = {
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addr[13] ? (~addr[2] ? ~data_in[0] : data_in[0]) : ~data_in[7],
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data_in[2],
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data_in[5],
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data_in[1],
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data_in[3],
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data_in[6],
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data_in[4],
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addr[13] ? (~addr[2] ? ~data_in[7] : data_in[7]) : ~data_in[0]
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};
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endcase
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end
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endmodule
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