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Arcade-Freeze_MiSTer/rtl/mcpu/decrypt.v
Pierre Cornier 78539ab907 first commit
2023-03-27 14:30:51 +02:00

38 lines
806 B
Verilog

module decrypt(
input [7:0] encryption,
input [7:0] data_in,
input [15:0] addr,
output reg [7:0] data_out
);
always @* begin
case (encryption)
8'd0: data_out = data_in;
8'd1: data_out = {
addr[13] ? (~addr[2] ? ~data_in[0] : data_in[0]) : ~data_in[7],
data_in[2],
data_in[5],
data_in[1],
data_in[3],
data_in[6],
data_in[4],
addr[13] ? (~addr[2] ? ~data_in[7] : data_in[7]) : ~data_in[0]
};
8'd2: data_out = {
addr[13] ? (~addr[2] ? ~data_in[0] : data_in[0]) : ~data_in[7],
data_in[2],
data_in[5],
data_in[1],
data_in[3],
data_in[6],
data_in[4],
addr[13] ? (~addr[2] ? ~data_in[7] : data_in[7]) : ~data_in[0]
};
endcase
end
endmodule