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https://github.com/MiSTer-devel/Arcade-Freeze_MiSTer.git
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102 lines
2.5 KiB
Verilog
102 lines
2.5 KiB
Verilog
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module decode(
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input [15:0] mcpu_ab,
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input [15:0] scpu_ab,
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input scpu_io_en,
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output reg mcpu_rom1_en,
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output reg mcpu_rom2_en,
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output reg mcpu_ram_en,
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output reg mcpu_spram_en,
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output reg mcpu_sndlatch_en,
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output reg mcpu_dsw1_en,
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output reg mcpu_dsw2_en,
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output reg mcpu_in0_en,
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output reg mcpu_in1_en,
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output reg mcpu_in2_en,
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output reg mcpu_in3_en,
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output reg mcpu_flip_en,
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output reg mcpu_pal_en,
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output reg mcpu_vram_en,
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output reg mcpu_cram_en,
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output reg scpu_rom_en,
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output reg scpu_ram_en,
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output reg scpu_ay_data_en,
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output reg scpu_ay_addr_en
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);
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always @* begin
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mcpu_rom1_en = 0;
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mcpu_rom2_en = 0;
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mcpu_ram_en = 0;
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mcpu_spram_en = 0;
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mcpu_sndlatch_en = 0;
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mcpu_dsw1_en = 0;
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mcpu_dsw2_en = 0;
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mcpu_in0_en = 0;
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mcpu_in1_en = 0;
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mcpu_in2_en = 0;
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mcpu_in3_en = 0;
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mcpu_flip_en = 0;
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mcpu_pal_en = 0;
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mcpu_vram_en = 0;
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mcpu_cram_en = 0;
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scpu_rom_en = 0;
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scpu_ram_en = 0;
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scpu_ay_data_en = 0;
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scpu_ay_addr_en = 0;
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if (mcpu_ab < 16'h4000) begin
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mcpu_rom1_en = 1;
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end else if (mcpu_ab >= 16'h4000 && mcpu_ab < 16'h6000) begin
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mcpu_ram_en = 1;
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end else if (mcpu_ab >= 16'hb000 && mcpu_ab < 16'hb080) begin
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mcpu_spram_en = 1;
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end else if (mcpu_ab == 16'hb400) begin
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mcpu_sndlatch_en = 1;
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end else if (mcpu_ab == 16'hb500) begin
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mcpu_dsw1_en = 1;
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end else if (mcpu_ab == 16'hb501) begin
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mcpu_dsw2_en = 1;
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end else if (mcpu_ab == 16'hb502) begin
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mcpu_in0_en = 1;
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end else if (mcpu_ab == 16'hb503) begin
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mcpu_in1_en = 1;
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end else if (mcpu_ab == 16'hb504) begin
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mcpu_in2_en = 1;
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end else if (mcpu_ab == 16'hb505) begin
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mcpu_in3_en = 1;
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end else if (mcpu_ab >= 16'hb506 && mcpu_ab < 16'hb508) begin
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mcpu_flip_en = 1;
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end else if (mcpu_ab >= 16'hb600 && mcpu_ab < 16'hb620) begin
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mcpu_pal_en = 1;
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end else if (mcpu_ab >= 16'hb800 && mcpu_ab < 16'hbc00) begin
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mcpu_vram_en = 1;
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end else if (mcpu_ab >= 16'hbc00 && mcpu_ab < 16'hc000) begin
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mcpu_cram_en = 1;
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end else if (mcpu_ab >= 16'hc000) begin
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mcpu_rom2_en = 1;
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end
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if (scpu_io_en) begin
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if (scpu_ab[7:0] == 8'h40) begin
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scpu_ay_data_en = 1;
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end else if (scpu_ab[7:0] == 8'h80) begin
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scpu_ay_addr_en = 1;
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end
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end
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else begin
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if (scpu_ab < 16'h2000) begin
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scpu_rom_en = 1;
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end else if (scpu_ab >= 16'h4000 && scpu_ab < 16'h6000) begin
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scpu_ram_en = 1;
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end
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end
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end
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endmodule
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