mirror of
https://github.com/MiSTer-devel/Arcade-Freeze_MiSTer.git
synced 2026-05-24 03:01:47 +00:00
307 lines
7.6 KiB
Verilog
307 lines
7.6 KiB
Verilog
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module core(
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input reset,
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input clk_sys,
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input [7:0] dsw1,
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input [7:0] dsw2,
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input [7:0] p0,
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input [7:0] p1,
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input [7:0] p2,
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input [7:0] p3,
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output [2:0] red,
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output [2:0] green,
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output [1:0] blue,
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output hb,
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output vb,
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output hs,
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output vs,
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output ce_pix,
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output [9:0] sound,
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input ioctl_download,
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input [26:0] ioctl_addr,
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input [15:0] ioctl_dout,
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input ioctl_wr
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// input [7:0] encryption
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);
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wire [15:0] mcpu_ab;
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wire [7:0] mcpu_din;
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wire [7:0] mcpu_dout;
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wire mcpu_rd;
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wire mcpu_wr;
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wire mcpu_io;
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wire mcpu_m1;
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wire [15:0] scpu_ab;
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wire [7:0] scpu_din;
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wire [7:0] scpu_dout;
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wire scpu_rd;
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wire scpu_wr;
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wire scpu_io;
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wire scpu_m1;
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// enable signals
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wire scpu_io_en = scpu_io;
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wire mcpu_rom1_en;
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wire mcpu_rom2_en;
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wire mcpu_ram_en;
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wire mcpu_spram_en;
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wire mcpu_sndlatch_en;
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wire mcpu_dsw1_en;
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wire mcpu_dsw2_en;
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wire mcpu_in0_en;
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wire mcpu_in1_en;
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wire mcpu_in2_en;
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wire mcpu_in3_en;
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wire mcpu_flip_en;
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wire mcpu_pal_en;
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wire mcpu_vram_en;
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wire mcpu_cram_en;
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wire scpu_rom_en;
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wire scpu_ram_en;
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wire scpu_ay_data_en;
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wire scpu_ay_addr_en;
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wire [7:0] mcpu_rom1_data;
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wire [7:0] mcpu_rom2_data;
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wire [7:0] mcpu_ram_data;
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wire [7:0] mcpu_vdata;
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reg [7:0] mcpu_sndlatch;
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wire [7:0] scpu_rom_data;
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wire [7:0] scpu_ram_data;
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reg scpu_int;
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wire [12:0] char_rom_addr;
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wire [7:0] char_data1;
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wire [7:0] char_data2;
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wire [12:0] spr_rom_addr;
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wire [7:0] spr_data1;
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wire [7:0] spr_data2;
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reg [3:0] ay_addr;
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wire [7:0] ay_dout;
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wire mcpu_vdata_en = mcpu_vram_en | mcpu_cram_en | mcpu_spram_en;
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wire [7:0] decrypt_data_out;
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assign mcpu_din =
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mcpu_in0_en ? p0 :
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mcpu_in1_en ? p1 :
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mcpu_in2_en ? p2 :
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mcpu_in3_en ? p3 :
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mcpu_dsw1_en ? dsw1 :
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mcpu_dsw2_en ? dsw2 :
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mcpu_rom1_en ? decrypt_data_out :
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mcpu_rom2_en ? mcpu_rom2_data :
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mcpu_ram_en ? mcpu_ram_data :
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mcpu_vdata_en ? mcpu_vdata :
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8'd0;
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assign scpu_din =
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scpu_ram_en ? scpu_ram_data :
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scpu_rom_en ? scpu_rom_data :
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scpu_ay_data_en & scpu_rd ? ay_dout :
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8'd0;
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always @(posedge clk_sys) begin
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if (scpu_ay_addr_en) begin
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if (scpu_wr) ay_addr <= scpu_dout[3:0];
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end
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if (mcpu_sndlatch_en) begin
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mcpu_sndlatch <= mcpu_dout;
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scpu_int <= 1'b1;
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end
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else begin
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scpu_int <= 1'b0;
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end
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end
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decode decode(
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.mcpu_ab ( mcpu_ab ),
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.scpu_ab ( scpu_ab ),
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.scpu_io_en ( scpu_io_en ),
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.mcpu_rom1_en ( mcpu_rom1_en ),
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.mcpu_rom2_en ( mcpu_rom2_en ),
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.mcpu_ram_en ( mcpu_ram_en ),
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.mcpu_spram_en ( mcpu_spram_en ),
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.mcpu_sndlatch_en ( mcpu_sndlatch_en ),
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.mcpu_dsw1_en ( mcpu_dsw1_en ),
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.mcpu_dsw2_en ( mcpu_dsw2_en ),
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.mcpu_in0_en ( mcpu_in0_en ),
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.mcpu_in1_en ( mcpu_in1_en ),
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.mcpu_in2_en ( mcpu_in2_en ),
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.mcpu_in3_en ( mcpu_in3_en ),
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.mcpu_flip_en ( mcpu_flip_en ),
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.mcpu_pal_en ( mcpu_pal_en ),
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.mcpu_vram_en ( mcpu_vram_en ),
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.mcpu_cram_en ( mcpu_cram_en ),
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.scpu_rom_en ( scpu_rom_en ),
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.scpu_ram_en ( scpu_ram_en ),
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.scpu_ay_data_en ( scpu_ay_data_en ),
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.scpu_ay_addr_en ( scpu_ay_addr_en )
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);
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mcpu mcpu(
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.clk_sys ( clk_sys ),
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.reset ( reset ),
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.mcpu_din ( mcpu_din ),
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.mcpu_dout ( mcpu_dout ),
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.mcpu_ab ( mcpu_ab ),
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.mcpu_wr ( mcpu_wr ),
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.mcpu_rd ( mcpu_rd ),
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.mcpu_io ( mcpu_io ),
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.mcpu_m1 ( mcpu_m1 ),
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.vb ( vb )
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);
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scpu scpu(
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.clk_sys ( clk_sys ),
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.reset ( reset ),
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.scpu_din ( scpu_din ),
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.scpu_dout ( scpu_dout ),
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.scpu_ab ( scpu_ab ),
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.scpu_wr ( scpu_wr ),
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.scpu_rd ( scpu_rd ),
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.scpu_io ( scpu_io ),
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.scpu_m1 ( scpu_m1 ),
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.scpu_int ( scpu_int )
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);
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wire cen, cen_t;
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clk_en #(16-1) jt49_clk_en(clk_sys, cen);
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clk_en #(512) timer_clk_en(clk_sys, cen_t); // 512 seems not fast enough
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reg [7:0] timer;
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always @(posedge clk_sys)
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if (cen_t) timer <= timer + 1;
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jt49 u_jt49(
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.rst_n ( ~reset ),
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.clk ( clk_sys ),
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.clk_en ( cen ),
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.addr ( ay_addr ),
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.cs_n ( ~scpu_ay_data_en ),
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.wr_n ( ~(scpu_ay_data_en & scpu_wr) ),
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.din ( scpu_dout ),
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.sel ( 1'b0 ),
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.dout ( ay_dout ),
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.sound ( sound ),
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.IOA_in ( mcpu_sndlatch ),
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.IOB_in ( timer[7:0] )
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);
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decrypt decrypt(
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.encryption ( 1'b0 ),
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.data_in ( mcpu_rom1_data ),
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.addr ( mcpu_ab ),
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.data_out ( decrypt_data_out )
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);
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mcpu_rom1 mcpu_rom1(
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.clk_sys ( clk_sys ),
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.rom_data ( mcpu_rom1_data ),
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.cpu_ab ( mcpu_ab ),
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.ioctl_download ( ioctl_download ),
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout ),
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.ioctl_wr ( ioctl_wr )
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);
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mcpu_rom2 mcpu_rom2(
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.clk_sys ( clk_sys ),
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.rom_data ( mcpu_rom2_data ),
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.cpu_ab ( mcpu_ab ),
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.ioctl_download ( ioctl_download ),
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout ),
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.ioctl_wr ( ioctl_wr )
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);
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scpu_rom scpu_rom(
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.clk_sys ( clk_sys ),
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.rom_data ( scpu_rom_data ),
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.cpu_ab ( scpu_ab ),
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.ioctl_download ( ioctl_download ),
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout ),
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.ioctl_wr ( ioctl_wr )
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);
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ram #(13,8) mcpu_ram(
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.clk ( clk_sys ),
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.addr ( mcpu_ab[12:0] ),
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.din ( mcpu_dout ),
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.q ( mcpu_ram_data ),
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.rd_n ( ~mcpu_rd ),
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.wr_n ( ~mcpu_wr ),
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.ce_n ( ~mcpu_ram_en )
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);
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ram #(13,8) scpu_ram(
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.clk ( clk_sys ),
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.addr ( scpu_ab[12:0] ),
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.din ( scpu_dout ),
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.q ( scpu_ram_data ),
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.rd_n ( ~scpu_rd ),
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.wr_n ( ~scpu_wr ),
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.ce_n ( ~scpu_ram_en )
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);
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vdata u_vdata(
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.clk_sys ( clk_sys ),
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.char_rom_addr ( char_rom_addr ),
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.char_data1 ( char_data1 ),
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.char_data2 ( char_data2 ),
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.spr_rom_addr ( spr_rom_addr ),
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.spr_data1 ( spr_data1 ),
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.spr_data2 ( spr_data2 ),
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.ioctl_download ( ioctl_download ),
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.ioctl_addr ( ioctl_addr ),
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.ioctl_dout ( ioctl_dout ),
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.ioctl_wr ( ioctl_wr )
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);
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video video(
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.reset ( reset ),
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.clk_sys ( clk_sys ),
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.hb ( hb ),
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.vb ( vb ),
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.hs ( hs ),
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.vs ( vs ),
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.ce_pix ( ce_pix ),
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.mcpu_ab ( mcpu_ab ),
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.mcpu_data ( mcpu_dout ),
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.mcpu_wr ( mcpu_wr ),
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.mcpu_rd ( mcpu_rd ),
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.mcpu_vdata ( mcpu_vdata ),
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.mcpu_pal_en ( mcpu_pal_en ),
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.mcpu_spram_en ( mcpu_spram_en ),
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.mcpu_vram_en ( mcpu_vram_en ),
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.mcpu_cram_en ( mcpu_cram_en ),
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.mcpu_flip_en ( mcpu_flip_en ),
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.char_rom_addr ( char_rom_addr ),
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.char_data1 ( char_data1 ),
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.char_data2 ( char_data2 ),
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.spr_rom_addr ( spr_rom_addr ),
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.spr_data1 ( spr_data1 ),
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.spr_data2 ( spr_data2 ),
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.red ( red ),
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.green ( green ),
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.blue ( blue )
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);
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endmodule
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