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https://github.com/MiSTer-devel/Arcade-ExpressRaider_MiSTer.git
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91 lines
1.9 KiB
Verilog
91 lines
1.9 KiB
Verilog
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module er_decode(
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input [15:0] cpu_addr,
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output reg sram_cs,
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output reg vram_cs,
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output reg cram_cs,
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output reg rom_cs,
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output reg ds0_read,
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output reg ds1_read,
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output reg in1_read,
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output reg in2_read,
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output reg nmi_clear,
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output reg snd_write,
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output reg flp_write,
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output reg dma_swap,
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output reg bg_sel,
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output reg pdat_read,
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output reg psta_read,
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output reg pdat_write,
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output reg scx_write,
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output reg scy_write
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);
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always @* begin
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sram_cs = 0;
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vram_cs = 0;
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cram_cs = 0;
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rom_cs = 0;
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ds0_read = 0;
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ds1_read = 0;
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in1_read = 0;
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in2_read = 0;
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nmi_clear = 0;
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snd_write = 0;
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flp_write = 0;
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dma_swap = 0;
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bg_sel = 0;
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pdat_read = 0;
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psta_read = 0;
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pdat_write = 0;
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scx_write = 0;
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scy_write = 0;
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case (cpu_addr[15:14])
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0: begin
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case (cpu_addr[13:12])
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0: begin
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case (cpu_addr[11:9])
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3: sram_cs = 1;
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4, 5: vram_cs = 1;
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6, 7: cram_cs = 1;
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endcase
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end
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1: begin
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case (cpu_addr[1:0])
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0: ds0_read = 1;
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1: in1_read = 1;
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2: in2_read = 1;
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3: ds1_read = 1;
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endcase
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end
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2: begin
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if (~cpu_addr[11]) begin
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case (cpu_addr[1:0])
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0: nmi_clear = 1;
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1: snd_write = 1;
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2: flp_write = 1;
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3: dma_swap = 1;
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endcase
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end
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else begin
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if (~cpu_addr[2]) bg_sel = 1;
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case (cpu_addr[2:0])
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0: pdat_read = 1;
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1: psta_read = 1;
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4: scy_write = 1;
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5, 6: scx_write = 1;
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7: pdat_write = 1;
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endcase
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end
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end
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endcase
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end
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1, 2, 3: rom_cs = 1;
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endcase
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end
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endmodule
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