mirror of
https://github.com/MiSTer-devel/Arcade-ExpressRaider_MiSTer.git
synced 2026-05-17 03:02:08 +00:00
108 lines
1.9 KiB
Verilog
108 lines
1.9 KiB
Verilog
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// 6502 BUS CONTROLLER
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module CPU16(
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input reset,
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input clk,
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input cen,
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input SYNC,
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input VB,
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input RW,
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input [15:0] ABI, // from CPU
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output reg [15:0] ABO, // to PCB
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input [7:0] CPU_DBI, // from CPU
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output reg [7:0] CPU_DBO, // to CPU
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input [7:0] DBI, // from PCB
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output [7:0] DBO // to PCB
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);
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reg read_io0;
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reg read_io1;
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reg read_dat;
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reg [7:0] din;
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reg [15:0] PAB;
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wire [15:0] ABN = PAB + 16'd2;
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assign DBO = CPU_DBI;
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wire [7:0] RAM_Q;
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wire ram_en = ABI[15:9] < 2'd3;
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ram #(11,8) RAM(
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.clk ( clk ),
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.addr ( ABI[10:0] ),
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.din ( CPU_DBI ),
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.q ( RAM_Q ),
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.rd_n ( 1'b0 ),
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.wr_n ( RW | ~ram_en ),
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.ce_n ( ~ram_en )
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);
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always @* begin
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ABO = ABI;
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// decode vector addresses
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if (ABI[15:4] == 12'hfff) begin
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ABO[15:4] = ABI[15:4];
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ABO[3:0] = ABI[3:0] ^ 4'hd;
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end
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end
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always @(posedge cen) begin
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if (cen) begin
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CPU_DBO <= DBI | RAM_Q;
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if (DBI[0] & DBI[1] & SYNC) begin // illegal
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PAB <= ABI;
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if (DBI == 8'b0110_0111) begin
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CPU_DBO <= 8'hA9; // send lda
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read_io0 <= 1'b1;
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end
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else if (DBI == 8'b0100_1011) begin // 4b
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CPU_DBO <= 8'hA9; // send lda
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read_io1 <= 1'b1;
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end
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else if (DBI == 8'b1000_1111) begin
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// ???? write "din" to IO
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end
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else begin
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CPU_DBO <= 8'hEA; // send nop
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read_dat <= 1'b1;
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end
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end
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else if (read_io0) begin
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CPU_DBO <= 8'd0; // ???
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read_io0 <= 1'b0;
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end
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else if (read_io1) begin
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CPU_DBO <= { 6'd0, VB, 1'b0 };
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read_io1 <= 1'b0;
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end
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if (read_dat) begin
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read_dat <= 1'b0;
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din <= DBI;
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end
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end
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end
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endmodule
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