2025-12-09 09:12:33 +01:00
2022-11-21 11:04:25 +01:00
2024-05-26 14:36:23 -06:00
2023-04-03 13:15:48 +02:00
2025-12-09 15:05:08 +08:00
2022-11-10 08:56:59 +01:00
2022-11-21 11:04:25 +01:00
2022-11-21 11:04:25 +01:00
2022-11-21 11:04:25 +01:00
2022-11-21 11:04:25 +01:00
2025-12-09 15:05:08 +08:00
2022-11-10 08:56:59 +01:00
2022-11-21 11:04:25 +01:00
2022-11-10 08:56:59 +01:00
2022-11-21 11:04:25 +01:00

Express Raider core for MiSTer

General description

This core is a port of Express Raider PCB from Data East USA by Pierco. I tried to stay as close as possible to the original schematics.

Thanks to my supporters!!

...and friends and the great MiSTer community!

Adrian Vargerson - Alan Steremberg - Allen Tipper - Amosfear - Andreas Micklei - Boogermann - Christopher Garland - Cory Stargel - Cyril Despontin - Cyrille Jouineau - Darren Chell - Darren Newman - Dave Ely - Davide Lorigliola - dECKARD - Dimitris Zongas - Francois P - Funkycochise - Grumpy Old Gamer - Herbert Krammer - Hiddenbyleaves - Holger Lagerfeldt - Humanoide70 - J BG - Johan Sjöstrand - John Stringer - José López Navarrete - Juan Carlos Pastor (Denymetanol) - Manuel Gomez Grande - Matt Hargett - Max - Michael Fuerst - Michael Packard - Mike Holzinger - Mike S - MiSTerFPGA.co.uk - Nicolas VAILLANT - Philip Lawson - Pons Cremator - RaspberryAlpine - Rune P - Samuel Giroux - Tonton Kaloun - Tony Escobar - wwark - yomitron

Description
Express Raider - MiSTer FPGA core
Readme GPL-2.0 8.2 MiB
Languages
Verilog 77%
SystemVerilog 12.6%
VHDL 8.6%
Tcl 1.7%