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https://github.com/MiSTer-devel/Arcade-Defender_MiSTer.git
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512 lines
13 KiB
Systemverilog
512 lines
13 KiB
Systemverilog
//============================================================================
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// Arcade: Defender
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//
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// Port to MiSTer
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// Copyright (C) 2017 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [48:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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output VGA_DISABLE, // analog out is off
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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output HDMI_BLACKOUT,
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output HDMI_BOB_DEINT,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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///////// Default values for ports not used in this core /////////
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assign ADC_BUS = 'Z;
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign VGA_F1 = 0;
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assign VGA_SCALER =0;
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assign AUDIO_MIX = 0;
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assign LED_USER = ioctl_download;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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assign FB_FORCE_BLANK = '0;
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assign HDMI_FREEZE = 0;
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assign HDMI_BLACKOUT = 0;
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assign HDMI_BOB_DEINT = 0;
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assign VGA_DISABLE = 0;
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wire [1:0] ar = status[17:16];
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assign VIDEO_ARX = (!ar) ? ((status[2] | landscape) ? 8'd4 : 8'd3) : (ar - 1'd1);
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assign VIDEO_ARY = (!ar) ? ((status[2] | landscape) ? 8'd3 : 8'd4) : 12'd0;
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`include "build_id.v"
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localparam CONF_STR = {
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"A.DFNDR;;",
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"-;",
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"H0OGH,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
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"H1H0O2,Orientation,Vert,Horz;",
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"O35,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
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"-;",
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"h2O67,Control,Mode 1,Mode 2,Cabinet;",
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"h2-;",
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"DIP;",
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"-;",
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"h2OR,Autosave Hiscores,Off,On;",
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"P1,Pause options;",
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"P1OP,Pause when OSD is open,On,Off;",
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"P1OQ,Dim video after 10s,On,Off;",
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"-;",
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"R0,Reset;",
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"J1,Fire 1,Fire 2,Fire 3,Fire 4,Fire 5,Start 1P,Start 2P,Coin,Advance,Auto Up,High Score Reset,Pause;",
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"V,v",`BUILD_DATE
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};
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//////////////////// CLOCKS ///////////////////
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wire clk_sys, clk_6, clk_48;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_48), // 48
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.outclk_1(clk_sys), // 24
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.outclk_2(clk_6) // 6
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);
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///////////////////////////////////////////////////
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wire [31:0] status;
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wire [1:0] buttons;
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wire forced_scandoubler;
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wire direct_video;
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wire ioctl_download;
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wire ioctl_upload;
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wire ioctl_upload_req;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_dout;
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wire [7:0] ioctl_din;
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wire [7:0] ioctl_index;
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wire [7:0] ioctl_data;
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wire ioctl_wait;
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wire [31:0] joy1, joy2;
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wire [31:0] joy = joy1 | joy2;
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wire [21:0] gamma_bus;
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hps_io #(.CONF_STR(CONF_STR)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.buttons(buttons),
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.status(status),
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.status_menumask({mod == mod_defender,landscape,direct_video}),
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.forced_scandoubler(forced_scandoubler),
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.gamma_bus(gamma_bus),
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.direct_video(direct_video),
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.video_rotated(video_rotated),
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.ioctl_download(ioctl_download),
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.ioctl_upload(ioctl_upload),
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.ioctl_upload_req(ioctl_upload_req),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.ioctl_din(ioctl_din),
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.ioctl_index(ioctl_index),
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.ioctl_wait(ioctl_wait),
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.joystick_0(joy1),
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.joystick_1(joy2)
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);
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wire rom_download = ioctl_download && (ioctl_index == 8'd0);
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wire nvram_selected = ioctl_index == 8'd4;
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reg reset;
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always @(posedge clk_6) reset <= RESET | status[0] | buttons[1] | rom_download;
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///////////////////////////////////////////////////////////////////
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wire m_start1 = joy[9];
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wire m_start2 = joy[10];
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wire m_coin1 = joy[11];
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wire m_advance = joy[12];
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wire m_autoup = joy[13];
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wire m_highreset=joy[14];
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wire m_pause =joy[15];
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wire m_right1 = joy1[0];
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wire m_left1 = joy1[1];
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wire m_down1 = joy1[2];
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wire m_up1 = joy1[3];
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wire m_fire1a = joy1[4];
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wire m_fire1b = joy1[5];
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wire m_fire1c = joy1[6];
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wire m_fire1d = joy1[7];
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wire m_fire1e = joy1[8];
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wire m_right2 = joy2[0];
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wire m_left2 = joy2[1];
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wire m_down2 = joy2[2];
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wire m_up2 = joy2[3];
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wire m_fire2a = joy2[4];
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wire m_fire2b = joy2[5];
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wire m_fire2c = joy2[6];
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wire m_fire2d = joy2[7];
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wire m_fire2e = joy2[8];
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wire m_right = m_right1 | m_right2;
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wire m_left = m_left1 | m_left2;
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wire m_down = m_down1 | m_down2;
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wire m_up = m_up1 | m_up2;
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wire m_fire_a = m_fire1a | m_fire2a;
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wire m_fire_b = m_fire1b | m_fire2b;
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wire m_fire_c = m_fire1c | m_fire2c;
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wire m_fire_d = m_fire1d | m_fire2d;
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wire m_fire_e = m_fire1e | m_fire2e;
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// PAUSE SYSTEM
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wire pause_cpu;
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wire [7:0] rgb_out;
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pause #(3,3,2,6) pause (
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.*,
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.clk_sys(clk_6), // Use CPU clock rather than clk_sys to reduce timing issues
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.user_button(m_pause),
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.pause_request(hs_pause),
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.options(~status[26:25])
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);
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///////////////////////////////////////////////////////////////////
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localparam mod_defender = 0;
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localparam mod_colony7 = 1;
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localparam mod_mayday = 2;
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localparam mod_jin = 3;
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reg [7:0] mod = 0;
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always @(posedge clk_sys) if (ioctl_wr & (ioctl_index==1)) mod <= ioctl_dout;
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// load the DIPS
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reg [7:0] sw[8];
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always @(posedge clk_sys) if (ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3]) sw[ioctl_addr[2:0]] <= ioctl_dout;
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///////////////////////////////////////////////////////////////////
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reg [7:0] input0;
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reg [7:0] input1;
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reg [7:0] input2;
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reg mayday;
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reg landscape;
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reg rotate_ccw;
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reg extvbl;
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always @(posedge clk_sys) begin
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mayday <= 0;
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input0 <= { 3'b000, m_coin1, m_highreset,1'b0,m_advance,m_autoup};
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input1 <= 0;
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input2 <= 0;
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landscape <= 1;
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rotate_ccw <= 0;
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extvbl <= 0;
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case(mod)
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mod_defender:
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begin
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input1 <= { m_down, (status[7:6]==2'b10)? m_fire_e : ( status[7:6]==2'b01 ? (def_state ? m_right : m_left) : (m_left | m_right)), m_start1, m_start2, m_fire_d, m_fire_c, status[7:6]==2'b01 ? (def_state ? m_left : m_right) : m_fire_b, m_fire_a };
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input2 <= { 7'b000000, m_up };
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end
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mod_colony7:
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begin
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landscape <= 0;
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rotate_ccw <= 1;
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input1 <= { m_fire_b, m_fire_a, m_start1, m_start2, m_up, m_left, m_right, m_down };
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input2 <= { 7'b000000, m_fire_c };
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end
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mod_mayday:
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begin
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mayday <= 1;
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input1 <= { m_down, 1'b0, m_start1, m_start2, m_fire_b, m_fire_c, m_right, m_fire_a };
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input2 <= { 7'b000000, m_up };
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end
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mod_jin:
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begin
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landscape <= 0;
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extvbl <= 1;
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input1 <= { m_fire_b, m_fire_a, m_start1, m_start2, m_right, m_left, m_down, m_up };
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end
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default:;
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endcase
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end
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wire no_rotate = status[2] | direct_video | landscape;
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reg [7:0] in0,in1,in2;
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reg extvbl1, mayday1;
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always @(posedge clk_6) begin
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in0 <= sw[0] | input0;
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in1 <= sw[1] | input1;
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in2 <= sw[2] | input2;
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extvbl1 <= extvbl;
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mayday1 <= mayday;
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end
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///////////////////////////////////////////////////////////////////
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wire [2:0] r,g;
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wire [1:0] b;
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wire HSync, VSync;
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wire HBlank, VBlank;
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wire def_state;
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defender defender
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(
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.clock_6(clk_6),
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.reset(reset),
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.pause(pause_cpu),
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.defender_state(def_state),
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.dn_clk(clk_sys),
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.dn_addr(ioctl_download ? ioctl_addr[15:0] : hs_address),
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.dn_data(ioctl_dout),
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.dn_wr(ioctl_wr & rom_download),
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.dn_nvram_wr(ioctl_wr & nvram_selected),
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.dn_din(hs_data_out),
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.dn_nvram(nvram_selected),
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.video_r(r),
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.video_g(g),
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.video_b(b),
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.video_hblank(HBlank),
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.video_vblank(VBlank),
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.video_hs(HSync),
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.video_vs(VSync),
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.audio_out(audio),
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.extvbl(extvbl1),
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.mayday(mayday1),
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.input0(in0),
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.input1(in1),
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.input2(in2)
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);
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///////////////////////////////////////////////////////////////////
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reg ce_pix;
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always @(posedge clk_48) begin
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reg [2:0] div;
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div <= div + 1'd1;
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ce_pix <= !div;
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end
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wire flip = 0;
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wire video_rotated;
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screen_rotate screen_rotate (.*);
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arcade_video #(306,8) arcade_video
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(
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.*,
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.clk_video(clk_48),
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.RGB_in(rgb_out),
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.fx(status[5:3])
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);
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wire [7:0] audio;
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assign AUDIO_L = {audio, audio[7:2]};
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assign AUDIO_R = AUDIO_L;
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assign AUDIO_S = 0;
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// HISCORE SYSTEM
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// --------------
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wire [7:0] hs_address;
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wire [7:0] hs_data_out;
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wire hs_pause;
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|
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nvram #(
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.DUMPWIDTH(8),
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.DUMPINDEX(4),
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.PAUSEPAD(2)
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) hi (
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.*,
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.clk(clk_sys),
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.paused(pause_cpu),
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.autosave(status[27]),
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.nvram_address(hs_address),
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.nvram_data_out(hs_data_out),
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.pause_cpu(hs_pause)
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|
);
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endmodule
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