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https://github.com/MiSTer-devel/Arcade-Dcon_MiSTer.git
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3ad6536176
D-Con (Success, 1992) — FPGA core for the MiSTer FPGA platform (Terasic DE10-Nano). Reimplements the original Seibu hardware in SystemVerilog from MAME (seibu/dcon.cpp, seibu/seibu_crtc.cpp), hardware documentation, main 68000 ROM disassembly and observation of real PCB behavior. Hardware emulated: - M68000 main CPU @ 10 MHz (FX68K cycle-accurate) - Z80 sound CPU @ 4 MHz (T80s) with audio-rate multicycle SDC - YM3812 OPL2 FM (jtopl2) + OKI M6295 ADPCM (jt6295) - 320x224 active video area (Seibu D-Con timings) - BG / MG / FG tilemaps + Text layer + 16x16 sprites (SEI0211) - Seibu CRTC registers (scroll, layer enable, flip screen) - xBGR_555 palette, 2048 entries Includes: - 16 SystemVerilog RTL files in rtl/DCon/ - FX68K core (rtl/fx68k/), audio cores (rtl/sound/jtopl, jt6295, t80) - JTFRAME framework subset (rtl/jtframe/), Sorgelig SDRAM bridge - MiSTer sys/ framework (HPS_IO, OSD, video scaler, audio) - Pause overlay with logo, supporters list and patron scroll - Quartus project files (DCon.qpf/qsf/sdc) - Prebuilt RBF (releases/DCon_20260530.rbf) and parent MRA - 6 in-game screenshots in docs/ Licensed under GNU GPL v3 or later. ROMs not included.
35 lines
3.1 KiB
Plaintext
35 lines
3.1 KiB
Plaintext
set_global_assignment -name QIP_FILE [join [list $::quartus(qip_path) pll_q [regexp -inline {[0-9]+} $quartus(version)] .qip] {}]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
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set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) math.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) shadowmask.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freak.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freezer.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) yc_out.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) iir_filter.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) f2sdram_safe_terminator.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hps_io.sv ]
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