mirror of
https://github.com/MiSTer-devel/Arcade-Dcon_MiSTer.git
synced 2026-05-31 03:02:21 +00:00
3ad6536176
D-Con (Success, 1992) — FPGA core for the MiSTer FPGA platform (Terasic DE10-Nano). Reimplements the original Seibu hardware in SystemVerilog from MAME (seibu/dcon.cpp, seibu/seibu_crtc.cpp), hardware documentation, main 68000 ROM disassembly and observation of real PCB behavior. Hardware emulated: - M68000 main CPU @ 10 MHz (FX68K cycle-accurate) - Z80 sound CPU @ 4 MHz (T80s) with audio-rate multicycle SDC - YM3812 OPL2 FM (jtopl2) + OKI M6295 ADPCM (jt6295) - 320x224 active video area (Seibu D-Con timings) - BG / MG / FG tilemaps + Text layer + 16x16 sprites (SEI0211) - Seibu CRTC registers (scroll, layer enable, flip screen) - xBGR_555 palette, 2048 entries Includes: - 16 SystemVerilog RTL files in rtl/DCon/ - FX68K core (rtl/fx68k/), audio cores (rtl/sound/jtopl, jt6295, t80) - JTFRAME framework subset (rtl/jtframe/), Sorgelig SDRAM bridge - MiSTer sys/ framework (HPS_IO, OSD, video scaler, audio) - Pause overlay with logo, supporters list and patron scroll - Quartus project files (DCon.qpf/qsf/sdc) - Prebuilt RBF (releases/DCon_20260530.rbf) and parent MRA - 6 in-game screenshots in docs/ Licensed under GNU GPL v3 or later. ROMs not included.
110 lines
1.9 KiB
Systemverilog
110 lines
1.9 KiB
Systemverilog
|
|
// result = num/div
|
|
module sys_udiv
|
|
#(
|
|
parameter NB_NUM,
|
|
parameter NB_DIV
|
|
)
|
|
(
|
|
input clk,
|
|
input start,
|
|
output busy,
|
|
|
|
input [NB_NUM-1:0] num,
|
|
input [NB_DIV-1:0] div,
|
|
output reg [NB_NUM-1:0] result,
|
|
output reg [NB_DIV-1:0] remainder
|
|
);
|
|
|
|
reg run;
|
|
assign busy = run;
|
|
|
|
always @(posedge clk) begin
|
|
reg [5:0] cpt;
|
|
reg [NB_NUM+NB_DIV+1:0] rem;
|
|
|
|
if (start) begin
|
|
cpt <= 0;
|
|
run <= 1;
|
|
rem <= num;
|
|
end
|
|
else if (run) begin
|
|
cpt <= cpt + 1'd1;
|
|
run <= (cpt != NB_NUM + 1'd1);
|
|
remainder <= rem[NB_NUM+NB_DIV:NB_NUM+1];
|
|
if (!rem[NB_DIV + NB_NUM + 1'd1])
|
|
rem <= {rem[NB_DIV+NB_NUM:0] - (div << NB_NUM),1'b0};
|
|
else
|
|
rem <= {rem[NB_DIV+NB_NUM:0] + (div << NB_NUM),1'b0};
|
|
result <= {result[NB_NUM-2:0], !rem[NB_DIV + NB_NUM + 1'd1]};
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
// result = mul1*mul2
|
|
module sys_umul
|
|
#(
|
|
parameter NB_MUL1,
|
|
parameter NB_MUL2
|
|
)
|
|
(
|
|
input clk,
|
|
input start,
|
|
output busy,
|
|
|
|
input [NB_MUL1-1:0] mul1,
|
|
input [NB_MUL2-1:0] mul2,
|
|
output reg [NB_MUL1+NB_MUL2-1:0] result
|
|
);
|
|
|
|
reg run;
|
|
assign busy = run;
|
|
|
|
always @(posedge clk) begin
|
|
reg [NB_MUL1+NB_MUL2-1:0] add;
|
|
reg [NB_MUL2-1:0] map;
|
|
|
|
if (start) begin
|
|
run <= 1;
|
|
result <= 0;
|
|
add <= mul1;
|
|
map <= mul2;
|
|
end
|
|
else if (run) begin
|
|
if(!map) run <= 0;
|
|
if(map[0]) result <= result + add;
|
|
add <= add << 1;
|
|
map <= map >> 1;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
// result = (mul1*mul2)/div
|
|
module sys_umuldiv
|
|
#(
|
|
parameter NB_MUL1,
|
|
parameter NB_MUL2,
|
|
parameter NB_DIV
|
|
)
|
|
(
|
|
input clk,
|
|
input start,
|
|
output busy,
|
|
|
|
input [NB_MUL1-1:0] mul1,
|
|
input [NB_MUL2-1:0] mul2,
|
|
input [NB_DIV-1:0] div,
|
|
output [NB_MUL1+NB_MUL2-1:0] result,
|
|
output [NB_DIV-1:0] remainder
|
|
);
|
|
|
|
wire mul_run;
|
|
wire [NB_MUL1+NB_MUL2-1:0] mul_res;
|
|
sys_umul #(NB_MUL1,NB_MUL2) umul(clk,start,mul_run,mul1,mul2,mul_res);
|
|
|
|
sys_udiv #(NB_MUL1+NB_MUL2,NB_DIV) udiv(clk,start|mul_run,busy,mul_res,div,result,remainder);
|
|
|
|
endmodule
|