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D-Con (Success, 1992) — FPGA core for the MiSTer FPGA platform (Terasic DE10-Nano). Reimplements the original Seibu hardware in SystemVerilog from MAME (seibu/dcon.cpp, seibu/seibu_crtc.cpp), hardware documentation, main 68000 ROM disassembly and observation of real PCB behavior. Hardware emulated: - M68000 main CPU @ 10 MHz (FX68K cycle-accurate) - Z80 sound CPU @ 4 MHz (T80s) with audio-rate multicycle SDC - YM3812 OPL2 FM (jtopl2) + OKI M6295 ADPCM (jt6295) - 320x224 active video area (Seibu D-Con timings) - BG / MG / FG tilemaps + Text layer + 16x16 sprites (SEI0211) - Seibu CRTC registers (scroll, layer enable, flip screen) - xBGR_555 palette, 2048 entries Includes: - 16 SystemVerilog RTL files in rtl/DCon/ - FX68K core (rtl/fx68k/), audio cores (rtl/sound/jtopl, jt6295, t80) - JTFRAME framework subset (rtl/jtframe/), Sorgelig SDRAM bridge - MiSTer sys/ framework (HPS_IO, OSD, video scaler, audio) - Pause overlay with logo, supporters list and patron scroll - Quartus project files (DCon.qpf/qsf/sdc) - Prebuilt RBF (releases/DCon_20260530.rbf) and parent MRA - 6 in-game screenshots in docs/ Licensed under GNU GPL v3 or later. ROMs not included.