mirror of
https://github.com/MiSTer-devel/Arcade-CongoBongo_MiSTer.git
synced 2026-05-24 03:01:44 +00:00
193 lines
6.0 KiB
VHDL
193 lines
6.0 KiB
VHDL
----------------
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-- Wave player --
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-----------------
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-- Congo samples - start/stop addresses as stored in memory
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-- bass.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 2005 start: 44(x 2C) stop: 2050(x 802)
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-- congal.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 2003 start: 2094(x 82E) stop: 4098(x 1002)
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-- congah.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 1970 start: 4142(x 102E) stop: 6112(x 17E0)
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-- rim.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 373 start: 6156(x 180C) stop: 6530(x 1982)
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-- gorilla.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 4991 start: 6574(x 19AE) stop: 11566(x 2D2E)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity samples_player is
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port(
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clock_24 : in std_logic;
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reset : in std_logic;
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port_b : in std_logic_vector(7 downto 0);
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port_c : in std_logic_vector(7 downto 0);
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audio_out : out std_logic_vector(15 downto 0);
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wave_addr : buffer std_logic_vector(15 downto 0);
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wave_rd : out std_logic;
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wave_data : in std_logic_vector(7 downto 0)
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);
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end samples_player;
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architecture struct of samples_player is
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signal wav_clk_cnt : std_logic_vector(11 downto 0); -- 11kHz divider / sound# counter
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subtype snd_id_t is integer range 0 to 4;
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signal snd_id : snd_id_t;
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type snd_addr_t is array(snd_id_t) of std_logic_vector(15 downto 0);
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-- wave current addresses in memory
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signal snd_addrs : snd_addr_t;
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-- bass.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 2005 start: 44(x 2C) stop: 2050(x 802)
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-- congal.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 2003 start: 2094(x 82E) stop: 4098(x 1002)
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-- congah.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 1970 start: 4142(x 102E) stop: 6112(x 17E0)
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-- rim.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 373 start: 6156(x 180C) stop: 6530(x 1982)
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-- gorilla.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 4991 start: 6574(x 19AE) stop: 11566(x 2D2E)
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-- wave start addresses in memory
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signal snd_starts : snd_addr_t := (x"002C",x"082E",x"102E",x"180C",x"19AE");
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-- wave end addresses in memory
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signal snd_stops : snd_addr_t := (x"0800",x"1000",x"17DE",x"1980",x"2D2C");
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type snd_flag_t is array(snd_id_t) of std_logic;
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-- sound playing (once)
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signal snd_starteds : snd_flag_t := ('0','0','0','0','0');
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-- sound to be restarted
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signal snd_restarts : snd_flag_t := ('0','0','0','0','0');
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-- sound playing (loop)
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signal snd_continus : snd_flag_t := ('0','0','0','0','0');
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signal port_b_r : std_logic_vector(7 downto 0);
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signal port_c_r : std_logic_vector(7 downto 0);
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-- sum all sound
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signal audio_r, audio_sum : signed(18 downto 0);
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signal audio_vol : signed(15 downto 0);
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-- signal wave_addr : std_logic_vector(15 downto 0);
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-- signal wave_data : std_logic_vector( 7 downto 0);
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begin
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-- scan sound# from 0-4
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snd_id <= to_integer(unsigned(wav_clk_cnt(7 downto 5))) when wav_clk_cnt(11 downto 5) <= 4 else 0;
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audio_vol <= (signed('0'&wave_data)-to_signed(128,9))&"0000000"; -- congo samples memory is uint8
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-- wave player
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process (clock_24, reset)
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begin
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if reset='1' then
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wav_clk_cnt <= (others=>'0');
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else
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if rising_edge(clock_24) then
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port_b_r <= port_b;
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port_c_r <= port_c;
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-- sound triggers
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-- snd_continus : play loop as long as set
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-- snd_starteds : edge trigger start playing when currently stopped
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-- snd_restarts : edge trigger restart from beginning
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snd_starteds( 0) <= snd_starteds( 0) or (not(port_c(0)) and port_c_r(0)); -- bass
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-- snd_restarts( 0) <= snd_restarts( 0) or (not(port_c(0)) and port_c_r(0));
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snd_starteds( 1) <= snd_starteds( 1) or (not(port_c(1)) and port_c_r(1)); -- congal
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snd_starteds( 2) <= snd_starteds( 2) or (not(port_c(2)) and port_c_r(2)); -- congah
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snd_starteds( 3) <= snd_starteds( 3) or (not(port_c(3)) and port_c_r(3)); -- rim
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snd_starteds( 4) <= snd_starteds( 4) or (not(port_b(1)) and port_b_r(1)); -- gorilla
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-- 11.025kHz base tempo / high bits for scanning sound#
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if wav_clk_cnt = x"880" then -- divide 24MHz by 2176 => 11.025kHz
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wav_clk_cnt <= (others=>'0');
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-- latch final audio / reset sum
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audio_r <= audio_sum;
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audio_sum <= (others => '0');
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else
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wav_clk_cnt <= wav_clk_cnt + 1;
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end if;
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-- clip audio
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if audio_r(18 downto 1) > 32767 then
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audio_out <= x"7FFF";
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elsif audio_r(18 downto 1) < -32767 then
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audio_out <= x"8001";
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else
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audio_out <= std_logic_vector(audio_r(16 downto 1)+to_signed(32767,16));
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end if;
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-- sdram read trigger (and auto refresh period)
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if wav_clk_cnt(4 downto 0) = "00000" then wave_rd <= '1';end if;
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if wav_clk_cnt(4 downto 0) = "00010" then wave_rd <= '0';end if;
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-- select only useful cycles (0-4)
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-- remaing cycles unsued
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if wav_clk_cnt(11 downto 5) <= 4 then
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-- set sdram addr at begining of cycle
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if wav_clk_cnt(4 downto 0) = "00000" then
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wave_addr <= snd_addrs(snd_id);
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end if;
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-- sound# currently playing
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if (snd_starteds(snd_id) = '1' or snd_continus(snd_id) = '1' ) then
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-- get sound# sample and update next sound# address
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-- (next / restart)
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if wav_clk_cnt(4 downto 0) = "10000" then
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audio_sum <= audio_sum + audio_vol;
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if snd_restarts(snd_id) = '1' then
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snd_addrs(snd_id) <= snd_starts(snd_id);
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snd_restarts(snd_id) <= '0';
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else
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snd_addrs(snd_id) <= snd_addrs(snd_id) + 1;
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end if;
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end if;
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-- update next sound# address
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-- (stop / loop)
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if snd_addrs(snd_id) >= snd_stops(snd_id) then
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if snd_continus(snd_id) = '1' then
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snd_addrs(snd_id) <= snd_starts(snd_id);
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else
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snd_starteds(snd_id) <= '0';
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end if;
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end if;
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else
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-- sound# stopped set begin address
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snd_addrs(snd_id) <= snd_starts(snd_id);
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end if;
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end if;
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end if;
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end if;
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end process;
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-- samples data --
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--samples : entity work.congo_samples
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--port map(
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-- clk => clock_24,
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-- addr => wave_addr(13 downto 0),
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-- data => wave_data
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--);
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end struct; |