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https://github.com/MiSTer-devel/Arcade-ComputerSpace_MiSTer.git
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295 lines
9.4 KiB
VHDL
295 lines
9.4 KiB
VHDL
-----------------------------------------------------------------------------
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-- ORIGINAL SCAN COUNTERS, SYNC, BLANK, ENABLE, STARS --
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-- For use with Computer Space FPGA emulator. --
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-- Implemented as part of the Sync Star Board. --
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-- Emulates the original timing (sort of progressive NTSC) for: --
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-- > scan counter logic (horizontal and vertical scan counters) --
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-- > count enable/blanking --
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-- > sync out logic --
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-- > star generation circuit --
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-- --
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-- This entity is implementation agnostic --
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-- --
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-- v1.0 --
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-- by Mattias G, 2015 --
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-- Enjoy! --
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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library work;
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--80---------------------------------------------------------------------------|
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entity scan_counter is
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port(
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game_clk : in std_logic;
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hsync : out std_logic;
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vsync : out std_logic;
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star_video_out,
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count_enable : out std_logic:= '0';
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hblank, vblank : out std_logic;
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b2_12 : out std_logic;
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vertical, horizontal : out std_logic_vector (7 downto 0)
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);
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end scan_counter;
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architecture scan_counter_architecture of
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scan_counter is
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-- 8 bit counter used for star generation
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component v74161 is
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port ( CLK, CLRN, LDN, ENP, ENT : in std_logic;
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D : in unsigned (7 downto 0);
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Q : out unsigned (7 downto 0);
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RCO : out std_logic );
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end component;
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-- statemachine
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type STATE_TYPE is (sLINE, sSYNC_BLANK);
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signal state : STATE_TYPE := sSYNC_BLANK;
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-- signals for
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-- video signalling
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signal hcount : integer :=130;
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signal vcount : integer :=1;
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signal blank_buffer : std_logic ;
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signal hor_scan_q : std_logic_vector (7 downto 0)
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:= "10000010";
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signal ver_scan_q : std_logic_vector (7 downto 0)
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:= "00000001";
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--signal hblank, vblank : std_logic;
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-- signals for star generation logic
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signal b5_10, b1_6, b1_5, b1_4 : std_logic;
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signal b1_3, b1_2, b1_1,b1_9, b2_8 : std_logic;
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signal a1_7, a1_6, a1_4, a1_3, a1_2 : std_logic;
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signal a1_1, a1_9, b1_10, a1_15 : std_logic;
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signal SB_16 : std_logic;
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signal b2_6 : std_logic;
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-- initial value for count enable
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-- flip-flop
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signal c4_14 : std_logic :='1';
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-- iniital value for rco
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signal e1_15_old : std_logic :='0';
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signal e1_15 : std_logic :='0';
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-- scan counter signals
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signal d1_e1_9, c1_f1_9, c1_f1_2 : std_logic;
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signal e1_6, d1_4, d1_3 : std_logic;
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signal f1_15 : std_logic := '0';
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signal b2_4 : std_logic;
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signal h1_11 : std_logic;
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signal d1_13, d1_12 : std_logic;
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signal c1_11, c1_12, c1_14,
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f1_12, f1_13 : std_logic;
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signal star_enable : std_logic;
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----------------------------------------------------------------------------//
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begin
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b2_12 <= game_clk;
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b5_10 <= not game_clk;
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-----------------------------------------------------------------------------
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-- GENERATE SYNC SIGNAL AND SCAN COUNTER VALUES --
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-- --
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-- replaces/emulates scan counter logic, count enable/blanking: --
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-- 74161s; D1, E1, C1, F1 --
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-- 7476 C4 (pin 1,2,3,4, 14, 15,1 6) --
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-- 7404 B2 (pin 3,4 and pin 5,6) --
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-- 7400 H1 (pin 11,12,13) --
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-- --
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-- replaces/emulates sync out logic: --
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-- 7420 J2 (j2_12) --
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-- 7486 J1 (j1_3) --
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-- 7420 F2 (f2_8) --
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-- 7486 J1 (j1_11) --
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-----------------------------------------------------------------------------
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-- 5,842 mhz version
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-----------------------------------------------------------------------------
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-- SCAN COUNTER --
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-----------------------------------------------------------------------------
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process (game_clk)
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begin
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if rising_edge (game_clk) then
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case state is
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when sSYNC_BLANK =>
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star_enable <= '0';
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if hcount < 255 then
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hcount <= hcount + 1;
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hor_scan_q <= hor_scan_q + 1;
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if hcount = 159 then hsync <= '1'; end if;
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if hcount = 191 then hsync <= '0'; end if;
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else
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if vcount = 255 then -- DarFPGA 2017
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hcount <= 1; -- | fixed counters w.r.t schematics
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hor_scan_q <= "00000001"; -- | (coherent with motion board explanations)
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else -- |
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hcount <= 0;
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hor_scan_q <= "00000000";
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end if;
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c4_14 <= '1'; -- CE
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star_enable <= '1';
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state <= sLINE;
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hblank <= '0';
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end if;
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when sLINE =>
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if hcount < 255 then -- visible line
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hcount <= hcount + 1;
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hor_scan_q <= hor_scan_q + 1;
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else -- last pixel on visible line
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hcount <= 130; -- load value for blank&sync
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hor_scan_q <= "10000010";
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c4_14 <= '0'; -- BLANK (not CE)
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state <= sSYNC_BLANK;
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hblank <= '1';
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if vcount = 239 then vblank <= '1'; end if;
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if vcount = 244 then vsync <= '1'; end if;
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if vcount = 248 then vsync <= '0'; end if;
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if vcount < 254 then -- Increase vertical count
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vcount <= vcount + 1;
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ver_scan_q <= ver_scan_q +1;
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elsif vcount = 254 then
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vcount <= vcount + 1;
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ver_scan_q <= ver_scan_q +1;
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f1_15 <= '1';
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else
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vcount <= 1;
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vblank <= '0';
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ver_scan_q <= "00000001";
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f1_15 <= '0';
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star_enable <= '0';
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end if;
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end if;
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end case;
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end if;
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end process;
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d1_13 <= hor_scan_q(1);
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d1_12 <= hor_scan_q(2);
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c1_14 <= ver_scan_q(0);
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c1_12 <= ver_scan_q(2);
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c1_11 <= ver_scan_q(3);
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f1_13 <= ver_scan_q(5);
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f1_12 <= ver_scan_q(6);
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-----------------------------------------------------------------------------
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-- Clear signal to star generator --
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-----------------------------------------------------------------------------
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b2_6 <= not f1_15;
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-----------------------------------------------------------------------------
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-- CREATING THE SYNC SIGNAL --
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-----------------------------------------------------------------------------
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-- vsync <= vblank;
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-----------------------------------------------------------------------------
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-- COUNT ENABLE & BLANK --
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-----------------------------------------------------------------------------
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count_enable <= c4_14;
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--blank <= hblank or vblank;
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-----------------------------------------------------------------------------
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-- SCAN COUNTER VALUES --
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-----------------------------------------------------------------------------
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horizontal <= hor_scan_q;
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vertical <= ver_scan_q;
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-----------------------------------------------------------------------------
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-- GENERATE STAR VIDEO --
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-- Signetics 74161: B1 & A1 --
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-- using one 8-bit counter instead of two 4-bit counters --
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-- --
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-- Instead of using c4_14 to drive the ENT (b1_10) a separate enable --
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-- signal (star_enable) is used in order to overcome a "deviation" in the --
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-- Signetics 74161 chip, that Computer Space uses, from the "standard" --
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-- 74161 implementations. --
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-- The Signetics 74161 allows one counter increment when ENT is low, --
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-- in the case ENT goes low when the clock is also low. --
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-- "Standard" 74161 (eg TI and others) prohibits increments all the time --
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-- when ENT is low. --
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-- The star layout on screen is a result of this deviation in Signetics --
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-- implementation of the 74161 counter. A deviation that took a very long --
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-- time to uncover. It was not until measurement data from a real --
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-- Computer Space Board was compared with standard 74161 chip behaviour --
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-- that this piece of the puzzle was solved. --
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-- --
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-- The implementation uses standard 74161 logic and a work-around with a --
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-- delayed ENT signal (star_enable) --
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-----------------------------------------------------------------------------
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star_counter: v74161
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port map(
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clk => b5_10,
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clrn => b1_1,
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ldn => b1_9,
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enp => '1',
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ent => b1_10,
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D(7) => a1_6,
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D(6) => '0',
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D(5) => a1_4,
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D(4) => a1_3,
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D(3) => b1_6,
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D(2) => b1_5,
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D(1) => b1_4,
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D(0) => b1_3,
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rco => a1_15
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);
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b1_6 <= d1_13; -- equals to d1_13;
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b1_5 <= c1_12;
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b1_4 <= c1_11;
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b1_3 <= c1_14;
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b1_1 <= b2_6; -- rco for msb
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b1_9 <= b2_8;
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b1_10 <= star_enable; -- using an additional flag
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-- called star_enable
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-- (should be c4_14)
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-- to cater for the fact that
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-- the CS Signetics 74161 has
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-- an odd implementation of
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-- the standard 74161
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-- related to how ENT impact
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-- increment when ENT is set
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-- to low when clock is low
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a1_6 <= d1_12;
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a1_4 <= f1_13;
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a1_3 <= f1_12;
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b2_8 <= not a1_15;
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star_video_out <= a1_15;
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end scan_counter_architecture;
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