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57407191bb
City Connection (Jaleco 1985) for MiSTer FPGA. - MC6809 main + audio CPU, AY-3-8910 (jt49), YM2203 (jt03) - PCB-accurate 247x224 video (vs 240 shown by MAME) - Pause overlay with logo, supporters scroll, links - OSD: 5 scale options, audio volume 100-200%, clean pause - ROM sets: citycon (parent), citycona, cruisin (alternatives)
20 lines
990 B
Tcl
20 lines
990 B
Tcl
derive_pll_clocks
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derive_clock_uncertainty
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# ============================================================
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# City Connection multicycle paths
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#
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# clk_sys = 40 MHz (dalla PLL — MAME MASTER/2).
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# Main CPU 6809 (mc6809i) opera a ce_E/ce_Q a 1.25 MHz — 1 impulso ogni 32 clk.
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# Quindi tutte le path interne della CPU hanno 32 clk per chiudere (non 1).
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# Setup multicycle = 32 → 32× periodo di clk_sys (= 32 × 25 ns = 800 ns).
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# Hold multicycle = 31 (always N-1 per CE-gated design).
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# ============================================================
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set_multicycle_path -setup -from [get_registers {*mc6809i*}] -to [get_registers {*mc6809i*}] 32
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set_multicycle_path -hold -from [get_registers {*mc6809i*}] -to [get_registers {*mc6809i*}] 31
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# ============================================================
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# Palette fetch loop: pal_byte_phase toggle ogni clk. Non CE-gated.
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# Chiusura a 40 MHz (periodo 25 ns) — abbondante.
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# ============================================================
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