mirror of
https://github.com/MiSTer-devel/Arcade-ChinaGate_MiSTer.git
synced 2026-05-24 03:01:42 +00:00
d6d7cb3155
FPGA core for China Gate (Technos Japan, 1988) on MiSTer. Full game with audio, 2 ROM sets (US + JP), pause overlay with logo + supporters scroll, MiSTer OSD audio mixer. ROM sets: - China Gate (US) — chinagat - Sai Yu Gou Ma Roku (Japan) — saiyugou (alternative) Hardware: 2x HD63C09 main+sub @ 1.5MHz, Z80 sound @ 3.579545MHz, YM2151 + OKI M6295. Resolution 256x240 @ 57Hz. License: GPL-3.0-or-later
78 lines
3.5 KiB
Tcl
78 lines
3.5 KiB
Tcl
# Specify root clocks
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
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create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
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create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
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create_clock -period "10.0 MHz" [get_pins -compatibility_mode hdmi_i2c|out_clk] -name hdmi_sck
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derive_pll_clocks
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derive_clock_uncertainty
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# Decouple different clock groups (to simplify routing)
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set_clock_groups -exclusive \
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-group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \
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-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
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-group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] \
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-group [get_clocks { spi_sck}] \
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-group [get_clocks { hdmi_sck}] \
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-group [get_clocks { *|h2f_user0_clk}] \
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-group [get_clocks { FPGA_CLK1_50 }] \
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-group [get_clocks { FPGA_CLK2_50 }] \
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-group [get_clocks { FPGA_CLK3_50 }]
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set_false_path -from [get_ports {KEY*}]
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set_false_path -from [get_ports {BTN_*}]
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set_false_path -to [get_ports {LED_*}]
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set_false_path -to [get_ports {VGA_*}]
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set_false_path -from [get_ports {VGA_EN}]
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set_false_path -to [get_ports {AUDIO_SPDIF}]
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set_false_path -to [get_ports {AUDIO_L}]
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set_false_path -to [get_ports {AUDIO_R}]
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set_false_path -from {get_ports {SW[*]}}
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set_false_path -to {cfg[*]}
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set_false_path -from {cfg[*]}
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set_false_path -from {VSET[*]}
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set_false_path -to {wcalc[*] hcalc[*]}
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set_false_path -to {hdmi_width[*] hdmi_height[*]}
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set_false_path -to {deb_* btn_en btn_up}
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set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
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set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
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set_false_path -to {*_osd|v_cnt*}
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set_false_path -to {*_osd|v_osd_start*}
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set_false_path -to {*_osd|v_info_start*}
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set_false_path -to {*_osd|h_osd_start*}
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set_false_path -from {*_osd|v_osd_start*}
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set_false_path -from {*_osd|v_info_start*}
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set_false_path -from {*_osd|h_osd_start*}
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set_false_path -from {*_osd|rot*}
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set_false_path -from {*_osd|dsp_width*}
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set_false_path -to {*_osd|half}
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set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
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set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
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set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}
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set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}
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set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
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set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
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set_false_path -from {aflt_* acx* acy* areset* arc*}
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set_false_path -from {arx* ary*}
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set_false_path -from {vs_line*}
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set_false_path -from {ColorBurst_Range* PhaseInc* pal_en cvbs yc_en}
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set_false_path -from {ascal|o_ihsize*}
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set_false_path -from {ascal|o_ivsize*}
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set_false_path -from {ascal|o_format*}
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set_false_path -from {ascal|o_hdown}
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set_false_path -from {ascal|o_vdown}
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set_false_path -from {ascal|o_hmin* ascal|o_hmax* ascal|o_vmin* ascal|o_vmax* ascal|o_vrrmax* ascal|o_vrr}
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set_false_path -from {ascal|o_hdisp* ascal|o_vdisp*}
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set_false_path -from {ascal|o_htotal* ascal|o_vtotal*}
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set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}
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set_false_path -from {ascal|o_hsize* ascal|o_vsize*}
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set_false_path -from {mcp23009|flg_*}
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set_false_path -to {sysmem|fpga_interfaces|clocks_resets|f2h*}
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