mirror of
https://github.com/MiSTer-devel/Arcade-ChinaGate_MiSTer.git
synced 2026-05-24 03:01:42 +00:00
d6d7cb3155
FPGA core for China Gate (Technos Japan, 1988) on MiSTer. Full game with audio, 2 ROM sets (US + JP), pause overlay with logo + supporters scroll, MiSTer OSD audio mixer. ROM sets: - China Gate (US) — chinagat - Sai Yu Gou Ma Roku (Japan) — saiyugou (alternative) Hardware: 2x HD63C09 main+sub @ 1.5MHz, Z80 sound @ 3.579545MHz, YM2151 + OKI M6295. Resolution 256x240 @ 57Hz. License: GPL-3.0-or-later
35 lines
3.1 KiB
Plaintext
35 lines
3.1 KiB
Plaintext
set_global_assignment -name QIP_FILE [join [list $::quartus(qip_path) pll_q [regexp -inline {[0-9]+} $quartus(version)] .qip] {}]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
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set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) math.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) shadowmask.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freak.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freezer.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) yc_out.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) iir_filter.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) f2sdram_safe_terminator.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hps_io.sv ]
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