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56 lines
2.2 KiB
Verilog
56 lines
2.2 KiB
Verilog
/*
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* __ __ __ __ __ __
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* /\ "-.\ \ /\ \/\ \ /\ \ /\ \
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* \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
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* \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
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* \/_/ \/_/ \/_____/ \/_____/ \/_____/
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* ______ ______ __ ______ ______ ______
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* /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
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* \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
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* \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
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* \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
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*
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* https://joshbassett.info
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* https://twitter.com/nullobject
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* https://github.com/nullobject
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*
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* Copyright (c) 2021 Josh Bassett
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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// Synchronizes an asynchronous reset signal to a target clock domain.
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module reset_ctrl (
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input clk,
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input rst_i,
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output rst_o
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);
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(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg r1 = 1'b1;
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(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg r2 = 1'b1;
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always @(posedge clk) begin
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r1 <= rst_i;
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r2 <= r1;
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end
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assign rst_o = r2;
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endmodule
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