mirror of
https://github.com/MiSTer-devel/Arcade-BubSysROM_MiSTer.git
synced 2026-04-19 03:02:31 +00:00
452 lines
15 KiB
Systemverilog
452 lines
15 KiB
Systemverilog
//============================================================================
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [48:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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output VGA_DISABLE, // analog out is off
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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output HDMI_BLACKOUT,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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///////// Default values for ports not used in this core /////////
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assign ADC_BUS = 'Z;
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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///////////////////////////////////////////////////////////
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////// PLL
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////
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wire CLK72M, CLK57M;
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wire pll_locked;
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pll pll(
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.refclk (CLK_50M ),
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.rst (RESET ),
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.outclk_0 (CLK72M ),
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.outclk_1 (SDRAM_CLK ),
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.outclk_2 (CLK57M ),
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.locked (pll_locked )
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);
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///////////////////////////////////////////////////////////
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////// HPS_IO
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////
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// Status Bit Map:
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// Upper Lower
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// 0 1 2 3 4 5 6
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// 01234567890123456789012345678901 23456789012345678901234567890123
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// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
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// X XXXXXXX X XXXXXXXXXXXXXXXX
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wire [127:0] status; //status bits
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`include "build_id.v"
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localparam CONF_STR = {
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"BubSysROM;",
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"-;",
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"P1,Scaler Settings;",
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"P1-;",
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"P1O23,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
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"h0P1O4,Orientation,Horizontal,Vertical;",
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"P1O5,VGA Scaler,off,on;",
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"P1O68,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
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"-;",
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"P2,Game Settings;",
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"P2-;",
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"P2OA,Gamma,original,user;",
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"P2OCF,K5289 volume,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;",
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"P2OGJ,VLM volume,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;",
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"P2OKN,PSG1 volume,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;",
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"P2OOR,PSG2 volume,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;",
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"-;",
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"DIP;",
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"-;",
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"R0,Reset and close OSD;",
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"J1,Button 1,Button 2,Button 3,Coin,Start,Service;",
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"jn,A,B,X,R,Start,Select;",
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"V,v",`BUILD_DATE
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};
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//ioctl
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wire [15:0] ioctl_index;
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wire ioctl_download;
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wire [26:0] ioctl_addr;
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wire [7:0] ioctl_data;
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wire ioctl_wr;
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wire ioctl_wait;
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wire [1:0] buttons; //hardware button
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wire [15:0] joystick_0;
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wire [15:0] joystick_1;
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wire forced_scandoubler; //?
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wire [21:0] gamma_bus;
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wire direct_video;
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wire video_rotation; //output from the core
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hps_io #(.CONF_STR(CONF_STR)) hps_io
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(
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.clk_sys (CLK72M ),
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.HPS_BUS (HPS_BUS ),
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.EXT_BUS ( ),
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.buttons (buttons ),
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.status (status ),
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.status_in (128'h0 ),
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.status_menumask ({15'd0, video_rotation} ),
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.direct_video (direct_video ),
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.new_vmode (1'b0 ),
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.forced_scandoubler (forced_scandoubler ),
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.gamma_bus (gamma_bus ),
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.ioctl_download (ioctl_download ),
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.ioctl_upload ( ),
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.ioctl_upload_req (1'b0 ),
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.ioctl_wr (ioctl_wr ),
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.ioctl_addr (ioctl_addr ),
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.ioctl_dout (ioctl_data ),
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.ioctl_din ( ),
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.ioctl_index (ioctl_index ),
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.ioctl_wait (ioctl_wait ),
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.joystick_0 (joystick_0 ),
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.joystick_1 (joystick_1 )
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);
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///////////////////////////////////////////////////////////
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////// CORE
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////
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wire hsync, vsync;
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wire hblank, vblank;
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wire [4:0] video_r_5bpp, video_g_5bpp, video_b_5bpp; //need to use color conversion LUT
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wire vcen;
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wire master_reset = RESET | status[0] | buttons[1];
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assign AUDIO_S = 1'b1;
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assign AUDIO_MIX = 2'd0;
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BubSysROM_emu gameboard_top (
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.i_EMU_MCLK (CLK72M ),
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.i_EMU_SCLK (CLK57M ),
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.i_EMU_INITRST (RESET ),
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.i_EMU_SOFTRST (master_reset ),
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.o_HBLANK (hblank ),
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.o_VBLANK (vblank ),
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.o_HSYNC (hsync ),
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.o_VSYNC (vsync ),
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.o_VIDEO_CEN (vcen ),
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.o_VIDEO_DEN ( ),
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.o_VIDEO_ROT (video_rotation ),
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.o_VIDEO_R (video_r_5bpp ),
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.o_VIDEO_G (video_g_5bpp ),
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.o_VIDEO_B (video_b_5bpp ),
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.i_VOL (status[27:12] ),
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.o_SND_L (AUDIO_L ),
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.o_SND_R (AUDIO_R ),
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.i_JOYSTICK0 (joystick_0 ),
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.i_JOYSTICK1 (joystick_1 ),
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.ioctl_index (ioctl_index ),
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.ioctl_download (ioctl_download ),
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.ioctl_addr (ioctl_addr ),
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.ioctl_data (ioctl_data ),
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.ioctl_wr (ioctl_wr ),
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.ioctl_wait (ioctl_wait ),
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.sdram_dq (SDRAM_DQ ),
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.sdram_a (SDRAM_A ),
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.sdram_dqml (SDRAM_DQML ),
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.sdram_dqmh (SDRAM_DQMH ),
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.sdram_ba (SDRAM_BA ),
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.sdram_nwe (SDRAM_nWE ),
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.sdram_ncas (SDRAM_nCAS ),
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.sdram_nras (SDRAM_nRAS ),
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.sdram_ncs (SDRAM_nCS ),
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.sdram_cke (SDRAM_CKE ),
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.debug (LED_USER )
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);
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//Bubble System resistor network gamma LUT, caculated by MAME's resnet.cpp
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function [7:0] bubsys_gamma (input [4:0] bubsys_5bpp); begin
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case(bubsys_5bpp)
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5'd0 : bubsys_gamma = 8'h00;
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5'd1 : bubsys_gamma = 8'h01;
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5'd2 : bubsys_gamma = 8'h02;
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5'd3 : bubsys_gamma = 8'h04;
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5'd4 : bubsys_gamma = 8'h05;
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5'd5 : bubsys_gamma = 8'h06;
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5'd6 : bubsys_gamma = 8'h08;
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5'd7 : bubsys_gamma = 8'h09;
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5'd8 : bubsys_gamma = 8'h0B;
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5'd9 : bubsys_gamma = 8'h0D;
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5'd10: bubsys_gamma = 8'h0F;
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5'd11: bubsys_gamma = 8'h12;
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5'd12: bubsys_gamma = 8'h14;
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5'd13: bubsys_gamma = 8'h16;
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5'd14: bubsys_gamma = 8'h19;
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5'd15: bubsys_gamma = 8'h1C;
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5'd16: bubsys_gamma = 8'h21;
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5'd17: bubsys_gamma = 8'h24;
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5'd18: bubsys_gamma = 8'h29;
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5'd19: bubsys_gamma = 8'h2E;
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5'd20: bubsys_gamma = 8'h33;
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5'd21: bubsys_gamma = 8'h39;
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5'd22: bubsys_gamma = 8'h40;
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5'd23: bubsys_gamma = 8'h49;
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5'd24: bubsys_gamma = 8'h50;
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5'd25: bubsys_gamma = 8'h5B;
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5'd26: bubsys_gamma = 8'h68;
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5'd27: bubsys_gamma = 8'h78;
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5'd28: bubsys_gamma = 8'h8E;
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5'd29: bubsys_gamma = 8'hA8;
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5'd30: bubsys_gamma = 8'hCC;
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5'd31: bubsys_gamma = 8'hFF;
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endcase
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end endfunction
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wire [7:0] video_r_8bpp = status[10] ? {video_r_5bpp, 3'd0} : bubsys_gamma(video_r_5bpp);
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wire [7:0] video_g_8bpp = status[10] ? {video_g_5bpp, 3'd0} : bubsys_gamma(video_g_5bpp);
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wire [7:0] video_b_8bpp = status[10] ? {video_b_5bpp, 3'd0} : bubsys_gamma(video_b_5bpp);
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///////////////////////////////////////////////////////////
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////// SCALER
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////
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assign VGA_F1 = 0;
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assign VGA_SCALER = status[5];
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assign VGA_DISABLE = 0;
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assign HDMI_FREEZE = 0;
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assign HDMI_BLACKOUT = 0;
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wire [1:0] ar = status[3:2];
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wire no_rotate = direct_video | ~status[4];
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assign VIDEO_ARX = (!ar) ? no_rotate ? 12'd4 : 12'd3 : (ar - 1'd1);
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assign VIDEO_ARY = (!ar) ? no_rotate ? 12'd3 : 12'd4 : 12'd0;
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arcade_video #(256,24) arcade_video (
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.clk_video (CLK72M ),
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.ce_pix (vcen ),
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.RGB_in ({video_r_8bpp, video_g_8bpp, video_b_8bpp}),
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.HBlank (hblank ),
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.VBlank (vblank ),
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.HSync (hsync ),
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.VSync (vsync ),
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.CLK_VIDEO (CLK_VIDEO ),
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.CE_PIXEL (CE_PIXEL ),
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.VGA_R (VGA_R ),
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.VGA_G (VGA_G ),
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.VGA_B (VGA_B ),
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.VGA_HS (VGA_HS ),
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.VGA_VS (VGA_VS ),
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.VGA_DE (VGA_DE ),
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.VGA_SL (VGA_SL ),
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.fx (status[8:6] ), //3bit
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.forced_scandoubler (forced_scandoubler ),
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.gamma_bus (gamma_bus ) //22bit
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);
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reg flip = 1'b0;
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reg rotate_ccw = 1'b0;
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wire video_rotated;
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screen_rotate screen_rotate ( .* );
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endmodule
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