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https://github.com/MiSTer-devel/Arcade-Astrocade_MiSTer.git
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29 lines
1.7 KiB
Plaintext
29 lines
1.7 KiB
Plaintext
set_global_assignment -name QIP_FILE rtl/T80/T80.qip
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/ddram.sv
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set_global_assignment -name VHDL_FILE rtl/bally_rams.vhd
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set_global_assignment -name VHDL_FILE rtl/bally_io.vhd
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set_global_assignment -name VHDL_FILE rtl/bally_data.vhd
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set_global_assignment -name VHDL_FILE rtl/bally_col_pal.vhd
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set_global_assignment -name VHDL_FILE rtl/bally_pattern.vhd
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set_global_assignment -name VHDL_FILE rtl/bally_addr.vhd
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set_global_assignment -name VHDL_FILE rtl/bally_sparkle.vhd
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set_global_assignment -name VHDL_FILE rtl/bally_starpos.vhd
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set_global_assignment -name VHDL_FILE rtl/bally_lamps.vhd
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set_global_assignment -name VHDL_FILE rtl/bram.vhd
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set_global_assignment -name VHDL_FILE rtl/bally.vhd
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set_global_assignment -name VHDL_FILE rtl/ebases_control.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/gorf_samples.sv
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set_global_assignment -name VHDL_FILE rtl/gorf_samples_S.vhd
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set_global_assignment -name VHDL_FILE rtl/gorf_samples_D.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/wow_samples.sv
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set_global_assignment -name VHDL_FILE rtl/wow_samples_S.vhd
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set_global_assignment -name VHDL_FILE rtl/wow_samples_D.vhd
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set_global_assignment -name VHDL_FILE rtl/seawolf_gray_binary.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/seawolf_samples.sv
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set_global_assignment -name VHDL_FILE rtl/seawolf_samples_S.vhd
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set_global_assignment -name VHDL_FILE rtl/seawolf_samples_D.vhd
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set_global_assignment -name VHDL_FILE rtl/wow_control.vhd
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set_global_assignment -name VERILOG_FILE rtl/second_order_dac.v
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set_global_assignment -name SYSTEMVERILOG_FILE "Arcade-Astrocade.sv"
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