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42 lines
1.2 KiB
VHDL
42 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all,ieee.numeric_std.all;
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entity GRAY is
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port (
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clk : in std_logic;
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addr : in std_logic_vector(5 downto 0);
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data : out std_logic_vector(7 downto 0);
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posi : out std_logic_vector(11 downto 0)
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);
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end entity;
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architecture prom of GRAY is
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type gray is array(0 to 63) of std_logic_vector(7 downto 0);
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signal lookup: gray := (
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X"20",X"21",X"23",X"22",X"26",X"27",X"25",X"24",
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X"2c",X"2d",X"2f",X"2e",X"2a",X"2b",X"29",X"28",
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X"38",X"39",X"3b",X"3a",X"3e",X"3f",X"3d",X"3c",
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X"34",X"35",X"37",X"36",X"32",X"33",X"31",X"30",
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X"10",X"11",X"13",X"12",X"16",X"17",X"15",X"14",
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X"1c",X"1d",X"1f",X"1e",X"1a",X"1b",X"19",X"18",
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X"08",X"09",X"0b",X"0a",X"0e",X"0f",X"0d",X"0c",
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X"04",X"05",X"07",X"06",X"02",X"03",X"01",X"00");
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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-- Grays binary as expected by Seawolf
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data <= lookup(to_integer(unsigned(addr)));
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-- Screen position for scope
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if (addr(5) = '1') then
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posi <= std_logic_vector((unsigned(addr(5 downto 0)) * 10) - 40);
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else
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posi <= std_logic_vector((unsigned(addr(5 downto 0)) * 11) - 72);
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end if;
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end if;
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end process;
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end architecture;
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