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This commit is contained in:
Jamie Blanks
2022-03-19 15:13:37 -04:00
commit 34f4a15cfd
228 changed files with 43739 additions and 0 deletions
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.gitignore vendored Normal file
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db
greybox_tmp
incremental_db
output_files
simulation
hc_output
scaler
hps_isw_handoff
vip
*_sim
.qsys_edit
PLLJ_PLLSPE_INFO.txt
*.bak
*.orig
*.rej
*.qdf
*.rpt
*.smsg
*.summary
*.done
*.jdi
*.pin
*.sof
*.qws
*.ppf
*.ddb
build_id.v
c5_pin_model_dump.txt
*.sopcinfo
*.csv
*.f
*.cmp
*.sip
*.spd
*.bsf
*~
*.xml
*_netlist
*.cdf
**/.DS_Store

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QUARTUS_VERSION = "17.0"
PROJECT_REVISION = "AdventureVision"

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# --------------------------------------------------------------------------
#
# MiSTer project
#
# WARNING WARNING WARNING:
# Do not add files to project in Quartus IDE! It will mess this file!
# Add the files manually to files.qip file.
#
# --------------------------------------------------------------------------
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
set_global_assignment -name SEED 1
#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
#enable it only if 8bit indexed mode is used in core
#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1"
#do not enable DEBUG_NOHDMI in release!
#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1"
# disable bilinear filtering when downscaling
#set_global_assignment -name VERILOG_MACRO "MISTER_DOWNSCALE_NN=1"
# disable adaptive scanline filtering
#set_global_assignment -name VERILOG_MACRO "MISTER_DISABLE_ADAPTIVE=1"
source sys/sys.tcl
source sys/sys_analog.tcl
source files.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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derive_pll_clocks
derive_clock_uncertainty
# core specific constraints

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{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Synthesized away node \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|outclk_wire\[2\]\"" { } { } 0 14320 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(129): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(134): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(594): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_audio:pll_audio\|pll_audio_0002:pll_audio_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21074 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "cyclonev_pll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}

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//============================================================================
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module emu
(
//Master input clock
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [48:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
output [12:0] VIDEO_ARX,
output [12:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
output VGA_SCALER, // Force VGA scaler
input [11:0] HDMI_WIDTH,
input [11:0] HDMI_HEIGHT,
output HDMI_FREEZE,
`ifdef MISTER_FB
// Use framebuffer in DDRAM (USE_FB=1 in qsf)
// FB_FORMAT:
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
// [3] : 0=16bits 565 1=16bits 1555
// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
//
// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
output FB_EN,
output [4:0] FB_FORMAT,
output [11:0] FB_WIDTH,
output [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output FB_FORCE_BLANK,
`ifdef MISTER_FB_PALETTE
// Palette control for 8bit modes.
// Ignored for other video modes.
output FB_PAL_CLK,
output [7:0] FB_PAL_ADDR,
output [23:0] FB_PAL_DOUT,
input [23:0] FB_PAL_DIN,
output FB_PAL_WR,
`endif
`endif
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
// I/O board button press simulation (active high)
// b[1]: user button
// b[0]: osd button
output [1:0] BUTTONS,
input CLK_AUDIO, // 24.576 MHz
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
//ADC
inout [3:0] ADC_BUS,
//SD-SPI
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
//SDRAM interface with lower latency
output SDRAM_CLK,
output SDRAM_CKE,
output [12:0] SDRAM_A,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
`ifdef MISTER_DUAL_SDRAM
//Secondary SDRAM
//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
input SDRAM2_EN,
output SDRAM2_CLK,
output [12:0] SDRAM2_A,
output [1:0] SDRAM2_BA,
inout [15:0] SDRAM2_DQ,
output SDRAM2_nCS,
output SDRAM2_nCAS,
output SDRAM2_nRAS,
output SDRAM2_nWE,
`endif
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR,
// Open-drain User port.
// 0 - D+/RX
// 1 - D-/TX
// 2..6 - USR2..USR6
// Set USER_OUT to 1 to read from USER_IN.
input [6:0] USER_IN,
output [6:0] USER_OUT,
input OSD_STATUS
);
///////// Default values for ports not used in this core /////////
assign ADC_BUS = 'Z;
assign USER_OUT = '1;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
assign VGA_F1 = 0;
assign VGA_SCALER = 0;
assign HDMI_FREEZE = 0;
assign AUDIO_MIX = 0;
assign LED_USER = 0;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign BUTTONS = 0;
//////////////////////////////////////////////////////////////////
// Status Bit Map: (0..31 => "O", 32..63 => "o")
// 0 1 2 3 4 5 6
// 01234567890123456789012345678901 23456789012345678901234567890123
// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
// XXXXXXX XX
`include "build_id.v"
localparam CONF_STR = {
"AVision;;",
"-;",
"F1,BIN,Load Game;",
"-;",
"O89,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
"O46,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
"O23,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
"-;",
"O1,Simulate Mirror,Off,On;",
"-;",
"R0,Reset;",
"J1,1,2,3,4;",
"jn,X,A,B,Y;",
"jp,X,A,B,Y;;",
"V,v",`BUILD_DATE
};
wire forced_scandoubler;
wire [1:0] buttons;
wire [31:0] status;
wire [10:0] ps2_key;
wire ioctl_download;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire ioctl_wait;
wire ioctl_wr;
wire [7:0] ioctl_index;
wire [15:0] joystick0, joystick1;
wire [21:0] gamma_bus;
assign ioctl_wait = 0;
hps_io #(.CONF_STR(CONF_STR)) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.EXT_BUS(),
.gamma_bus(gamma_bus),
.ioctl_download(ioctl_download),
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout),
.ioctl_wait(ioctl_wait),
.ioctl_index(ioctl_index),
.joystick_0(joystick0),
.joystick_1(joystick1),
.forced_scandoubler(forced_scandoubler),
.buttons(buttons),
.status(status),
.status_menumask(0),
.ps2_key(ps2_key)
);
/////////////////////// CLOCKS ///////////////////////////////
wire clk_sys, clk_vid;
pll pll
(
.refclk(CLK_50M),
.rst(0),
.outclk_0(clk_sys),
.outclk_1(clk_vid)
);
wire reset = RESET | status[0] | buttons[1] | ioctl_download;
//////////////////////////////////////////////////////////////////
wire HBlank;
wire VBlank;
wire [1:0] av_audio;
wire [39:0] av_led_n;
wire av_disp_photo_int;
wire por_n;
wire [11:0] av_bus_a;
wire [7:0] av_cart_dout;
wire av_cart_select;
wire hsync_n, vsync_n;
wire [2:0] Red;
// av_audio(1) : volume 0 = high, 1 = low
// av_audio(0) : digital sound waveform
assign AUDIO_R = AUDIO_L;
assign AUDIO_S = 0;
assign AUDIO_L = {av_audio[0], (av_audio[1] ? 8'd0 : 12'd0)};
// Physical button layout
// 1 1
// 2 4 JS 4 2
// 3 3
// I'll assume the right buttons are considered primary
wire joy_up = ~joystick0[3] & ~joystick1[3];
wire joy_down = ~joystick0[2] & ~joystick1[2];
wire joy_left = ~joystick0[1] & ~joystick1[1];
wire joy_right = ~joystick0[0] & ~joystick1[0];
wire [7:0] vdd8_s = 8'hFF; // Simulate a pulled up expansion bus
av_machine AdventureVision
(
//-- System Interface -------------------------------------------------------
.clk_11m_i (clk_sys), //: in std_logic;
.reset_n_i (~reset), //: in std_logic;
.por_n_o (por_n), //: out std_logic;
//-- Cartridge Interface ----------------------------------------------------
.cart_a_o (av_bus_a), //: out std_logic_vector(11 downto 0);
.cart_oe_n_o (av_cart_select), //: out std_logic;
.cart_d_i (av_cart_dout), //: in std_logic_vector( 7 downto 0);
//-- Buttons and Stick Interface --------------------------------------------
.but_1_n_i (~joystick0[4] & ~joystick1[4]), //: in std_logic;
.but_2_n_i (~joystick0[5] & ~joystick1[5]), //: in std_logic;
.but_3_n_i (~joystick0[6] & ~joystick1[6]), //: in std_logic;
.but_4_n_i (~joystick0[7] & ~joystick1[7]), //: in std_logic;
.stick_l_n_i (joy_left), //: in std_logic;
.stick_r_n_i (joy_right), //: in std_logic;
.stick_u_n_i (joy_up), //: in std_logic;
.stick_d_n_i (joy_down), //: in std_logic;
//-- Sound Interface --------------------------------------------------------
.audio_o (av_audio), //: out std_logic_vector( 1 downto 0);
//-- Display Interface ------------------------------------------------------
.led_n_o (av_led_n), //: out std_logic_vector(39 downto 0);
.disp_p24_n_o (), //: out std_logic;
.disp_photo_int_o (av_disp_photo_int), //: out std_logic;
//-- Expansion Interface ----------------------------------------------------
.exp_t0_i (vdd8_s), //: in std_logic;
.exp_t0_o (), //: out std_logic;
.exp_t0_dir_o (), //: out std_logic;
.exp_rd_n_o (), //: out std_logic;
.exp_psen_n_o (), //: out std_logic;
.exp_wr_n_o (), //: out std_logic;
.exp_ale_o (), //: out std_logic;
.exp_d_i (vdd8_s), //: in std_logic_vector( 7 downto 0);
.exp_d_o (), //: out std_logic_vector( 7 downto 0);
.exp_p1_i (vdd8_s), //: in std_logic_vector( 7 downto 3);
.exp_p1_o (), //: out std_logic_vector( 7 downto 3);
.exp_p1_low_imp_o (), //: out std_logic;
.exp_p2_i (vdd8_s), //: in std_logic_vector( 3 downto 0);
.exp_p2_o (), //: out std_logic_vector( 3 downto 0);
.exp_p2l_low_imp_o (), //: out std_logic;
.exp_p2h_low_imp_o (), //: out std_logic;
.exp_prog_n_o () //: out std_logic
);
av_video #(.is_pal_g(0)) av_video
(
.clk_11m_i (clk_sys),
.por_n_i (por_n),
.disp_photo_int_i (av_disp_photo_int),
.led_n_i (av_led_n),
.rgb_r_o (Red),
.rgb_hsync_n_o (hsync_n),
.rgb_vsync_n_o (vsync_n),
.rgb_csync_n_o (),
.hblank (HBlank),
.vblank (VBlank),
.fixed_intensity (~status[1])
);
dpram #(.addr_width_g(12)) cart_ram
(
.clk_b_i (clk_sys),
.addr_b_i (av_bus_a),
.data_b_o (av_cart_dout),
.clk_a_i (clk_sys),
.addr_a_i (ioctl_addr),
.data_a_i (ioctl_dout),
.we_i (ioctl_wr)
);
wire [2:0] scale = status[6:4];
wire [2:0] sl = scale ? scale - 1'd1 : 3'd0;
wire HSync = ~hsync_n;
wire VSync = ~vsync_n;
typedef struct packed {
logic [7:0] Red;
logic VBlank;
logic VSync;
logic HBlank;
logic HSync;
logic ce_pix;
} video_t;
video_t [3:0] vid_pipe;
wire vid_de;
video_mixer #(.LINE_LENGTH(450),.GAMMA(1),.HALF_DEPTH(0)) video_mixer
(
.CLK_VIDEO (CLK_VIDEO), // should be multiple by (ce_pix*4)
.CE_PIXEL (CE_PIXEL), // output pixel clock enable
.ce_pix (vid_pipe[3].ce_pix), // input pixel clock or clock_enable
.scandoubler (scale || forced_scandoubler),
.hq2x (scale == 1), // high quality 2x scaling
.gamma_bus (gamma_bus),
.R (vid_pipe[3].Red),
.G (8'd0),
.B (8'd0),
.HSync (vid_pipe[3].HSync),
.VSync (vid_pipe[3].VSync),
.HBlank (vid_pipe[3].HBlank),
.VBlank (vid_pipe[3].VBlank),
.HDMI_FREEZE (),
.freeze_sync (),
.VGA_R (VGA_R),
.VGA_G (VGA_G),
.VGA_B (VGA_B),
.VGA_VS (VGA_VS),
.VGA_HS (VGA_HS),
.VGA_DE (vid_de)
);
wire [1:0] ar = status[9:8];
video_freak video_freak
(
.CLK_VIDEO (CLK_VIDEO),
.CE_PIXEL (CE_PIXEL),
.VGA_VS (VGA_VS),
.HDMI_WIDTH (HDMI_HEIGHT),
.HDMI_HEIGHT (HDMI_WIDTH),
.VGA_DE (VGA_DE),
.VIDEO_ARX (VIDEO_ARX),
.VIDEO_ARY (VIDEO_ARY),
.VGA_DE_IN (vid_de),
.ARX ((!ar) ? 12'd1387 : (ar - 1'd1)),
.ARY ((!ar) ? 12'd962 : 12'd0),
.CROP_SIZE (10'd0),
.CROP_OFF (0),
.SCALE (status[3:2])
);
reg [1:0] pix_div;
always @(posedge clk_vid) begin
pix_div <= pix_div + 1'd1;
vid_pipe[0].Red <= {Red, Red, Red[2:1]};
vid_pipe[0].HSync <= HSync;
vid_pipe[0].VSync <= VSync;
vid_pipe[0].HBlank <= HBlank;
vid_pipe[0].VBlank <= VBlank;
vid_pipe[0].ce_pix <= &pix_div;
vid_pipe[3:1] <= vid_pipe[2:0];
end
assign CLK_VIDEO = clk_vid;
assign VGA_SL = sl[1:0];
endmodule

2
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QUARTUS_VERSION = "13.1"
PROJECT_REVISION = "AdventureVision_Q13"

46
AdventureVision_Q13.qsf Normal file
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# --------------------------------------------------------------------------
#
# MiSTer project
#
# WARNING WARNING WARNING:
# Do not add files to project in Quartus IDE! It will mess this file!
# Add the files manually to files.qip file.
#
# --------------------------------------------------------------------------
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
set_global_assignment -name SEED 1
source sys/sys.tcl
source sys/sys_analog.tcl
set_global_assignment -name QIP_FILE files.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

28
AdventureVision_Q13.srf Normal file
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{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(209): object \"vip_newcfg\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL information at MC6845.v(280): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at sys_top.v(601): object \"VSET\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Dummy RLC values generated in IBIS model files for device 5CSEBA6 with package UFBGA and pin count 672" { } { } 0 205009 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(10): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(9): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(29): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Timing characteristics of device 5CSEBA6U23I7 are preliminary" { } { } 0 334000 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|rom_map_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(17): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(16): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored filter at sys_top.sdc(37): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 176250 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance pll_audio:pll_audio\|pll_audio_0002:pll_audio_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_audio:pll_audio\|pll_audio_0002:pll_audio_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}

340
COPYING Normal file
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@@ -0,0 +1,340 @@
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
the GNU Library General Public License instead.) You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
this service if you wish), that you receive source code or can get it
if you want it, that you can change the software or use pieces of it
in new free programs; and that you know you can do these things.
To protect your rights, we need to make restrictions that forbid
anyone to deny you these rights or to ask you to surrender the rights.
These restrictions translate to certain responsibilities for you if you
distribute copies of the software, or if you modify it.
For example, if you distribute copies of such a program, whether
gratis or for a fee, you must give the recipients all the rights that
you have. You must make sure that they, too, receive or can get the
source code. And you must show them these terms so they know their
rights.
We protect your rights with two steps: (1) copyright the software, and
(2) offer you this license which gives you legal permission to copy,
distribute and/or modify the software.
Also, for each author's protection and ours, we want to make certain
that everyone understands that there is no warranty for this free
software. If the software is modified by someone else and passed on, we
want its recipients to know that what they have is not the original, so
that any problems introduced by others will not reflect on the original
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Finally, any free program is threatened constantly by software
patents. We wish to avoid the danger that redistributors of a free
program will individually obtain patent licenses, in effect making the
program proprietary. To prevent this, we have made it clear that any
patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and
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GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
a notice placed by the copyright holder saying it may be distributed
under the terms of this General Public License. The "Program", below,
refers to any such program or work, and a "work based on the Program"
means either the Program or any derivative work under copyright law:
that is to say, a work containing the Program or a portion of it,
either verbatim or with modifications and/or translated into another
language. (Hereinafter, translation is included without limitation in
the term "modification".) Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not
covered by this License; they are outside its scope. The act of
running the Program is not restricted, and the output from the Program
is covered only if its contents constitute a work based on the
Program (independent of having been made by running the Program).
Whether that is true depends on what the Program does.
1. You may copy and distribute verbatim copies of the Program's
source code as you receive it, in any medium, provided that you
conspicuously and appropriately publish on each copy an appropriate
copyright notice and disclaimer of warranty; keep intact all the
notices that refer to this License and to the absence of any warranty;
and give any other recipients of the Program a copy of this License
along with the Program.
You may charge a fee for the physical act of transferring a copy, and
you may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion
of it, thus forming a work based on the Program, and copy and
distribute such modifications or work under the terms of Section 1
above, provided that you also meet all of these conditions:
a) You must cause the modified files to carry prominent notices
stating that you changed the files and the date of any change.
b) You must cause any work that you distribute or publish, that in
whole or in part contains or is derived from the Program or any
part thereof, to be licensed as a whole at no charge to all third
parties under the terms of this License.
c) If the modified program normally reads commands interactively
when run, you must cause it, when started running for such
interactive use in the most ordinary way, to print or display an
announcement including an appropriate copyright notice and a
notice that there is no warranty (or else, saying that you provide
a warranty) and that users may redistribute the program under
these conditions, and telling the user how to view a copy of this
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
themselves, then this License, and its terms, do not apply to those
sections when you distribute them as separate works. But when you
distribute the same sections as part of a whole which is a work based
on the Program, the distribution of the whole must be on the terms of
this License, whose permissions for other licensees extend to the
entire whole, and thus to each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest
your rights to work written entirely by you; rather, the intent is to
exercise the right to control the distribution of derivative or
collective works based on the Program.
In addition, mere aggregation of another work not based on the Program
with the Program (or with a work based on the Program) on a volume of
a storage or distribution medium does not bring the other work under
the scope of this License.
3. You may copy and distribute the Program (or a work based on it,
under Section 2) in object code or executable form under the terms of
Sections 1 and 2 above provided that you also do one of the following:
a) Accompany it with the complete corresponding machine-readable
source code, which must be distributed under the terms of Sections
1 and 2 above on a medium customarily used for software interchange; or,
b) Accompany it with a written offer, valid for at least three
years, to give any third party, for a charge no more than your
cost of physically performing source distribution, a complete
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distributed under the terms of Sections 1 and 2 above on a medium
customarily used for software interchange; or,
c) Accompany it with the information you received as to the offer
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allowed only for noncommercial distribution and only if you
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The source code for a work means the preferred form of the work for
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If distribution of executable or object code is made by offering
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distribution of the source code, even though third parties are not
compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense or distribute the Program is
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However, parties who have received copies, or rights, from you under
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5. You are not required to accept this License, since you have not
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license would not permit royalty-free redistribution of the Program by
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the only way you could satisfy both it and this License would be to
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If any portion of this section is held invalid or unenforceable under
any particular circumstance, the balance of the section is intended to
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It is not the purpose of this section to induce you to infringe any
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integrity of the free software distribution system, which is
implemented by public license practices. Many people have made
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This section is intended to make thoroughly clear what is believed to
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8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
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may add an explicit geographical distribution limitation excluding
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9. The Free Software Foundation may publish revised and/or new versions
of the General Public License from time to time. Such new versions will
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Foundation.
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NO WARRANTY
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FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
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TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
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REPAIR OR CORRECTION.
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WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) 19yy <name of author>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) 19yy name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Library General
Public License instead of this License.

11
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Redistribution and use in source and synthesized forms, with or without modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in synthesized form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of the author nor the names of other contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
See also the file COPYING.

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# Adventure Vision
## General Information
This is a port of the adventure vision core originally written by Arnim Laeuger in 2006. The system has 4 retail games, and two homebrew games. The core uses the folder AVision for its games, and no other setup is required.
## Technical Details
The screen of the Adventure Vision was a strip of 40 LEDs that reflected off a rapidly rotating mirror, similar to a grocery store scanner. This resulted in a 15 frames per second image of 150x40 pixels. The original system's display was extremely flickery as a result, and the shape of it "wobbled". The core has an option to try to emulate this, but it defaults to having the flicker off for comfort and safety. If you choose to try this feature, it seems to look best on very small CRTs.
## Button Layout
```
1 1
2 4 JS 4 2
3 3
```
There are two sets of buttons, intended for multiplayer, which have slightly different layouts. On the core, both the first and second player controllers will have full access to the controls.

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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
for /d %%i in (sys\*_sim) do rmdir /s /q "%%i"
for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del *.cdf
del *.rpt
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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set_global_assignment -name SDC_FILE AdventureVision.sdc
set_global_assignment -name SYSTEMVERILOG_FILE AdventureVision.sv
#set_global_assignment -name VHDL_FILE rtl/bram.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/t48_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/alu_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/cond_branch_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/decoder_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/dmem_ctrl_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/pmem_ctrl_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_opt_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/opc_table.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/t48_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_io_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_opc_table.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/opc_decoder.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/int.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_clkgen.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_reset.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_pmem_ctrl.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_dmem_ctrl.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_decoder.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_skip.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_alu.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_stack.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_io_l.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_io_d.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_io_g.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_io_in.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_sio.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_timer.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/alu.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/bus_mux.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/clock_ctrl.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/cond_branch.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/db_bus.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/decoder.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/dmem_ctrl.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/timer.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/p1.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/p2.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/pmem_ctrl.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/psw.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/tech/t400_tech_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_core.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/system/t410_rom-e.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/tech/generic/generic_ram_ena.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/tech/spartan/t400_por.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/t400_core_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/t48_core.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/system/syn_rom-e.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/system/syn_ram-e.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/t48_core_comp_pack-p.vhd
#set_global_assignment -name VHDL_FILE rtl/board/gamepads/snespad/rtl/vhdl/snespad_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/tech/generic/generic_ram.vhd
set_global_assignment -name VHDL_FILE rtl/tech/tech_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/system/t410_notri.vhd
set_global_assignment -name VHDL_FILE rtl/t400/rtl/vhdl/system/t400_system_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/tech/spartan/av_por.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/system/t8048_notri.vhd
set_global_assignment -name VHDL_FILE rtl/t48/rtl/vhdl/system/t48_system_comp_pack-p.vhd
#set_global_assignment -name VHDL_FILE rtl/board/gamepads/snespad/rtl/vhdl/snespad_ctrl.vhd
#set_global_assignment -name VHDL_FILE rtl/board/gamepads/snespad/rtl/vhdl/snespad_pad.vhd
set_global_assignment -name VHDL_FILE rtl/tech/generic/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/video/av_frame_buffer.vhd
set_global_assignment -name VHDL_FILE rtl/video/av_raster.vhd
set_global_assignment -name VHDL_FILE rtl/video/av_video_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/av_comp_pack-p.vhd
set_global_assignment -name VHDL_FILE rtl/av_main.vhd
set_global_assignment -name VHDL_FILE rtl/av_ctrl.vhd
set_global_assignment -name VHDL_FILE rtl/av_disp.vhd
set_global_assignment -name VHDL_FILE rtl/av_machine_comp_pack-p.vhd
#set_global_assignment -name VHDL_FILE rtl/board/misc/board_misc_comp_pack-p.vhd
#set_global_assignment -name VHDL_FILE rtl/board/gamepads/snespad/rtl/vhdl/snespad_comp-pack.vhd
#set_global_assignment -name VHDL_FILE rtl/board/zefant_xs3/zefant_xs3_pll.vhd
set_global_assignment -name VHDL_FILE rtl/av_machine.vhd
set_global_assignment -name VHDL_FILE rtl/video/av_video.vhd
#set_global_assignment -name VHDL_FILE rtl/board/misc/dblscan.vhd
#set_global_assignment -name VHDL_FILE rtl/board/misc/pcm_sound.vhd
#set_global_assignment -name VHDL_FILE rtl/board/gamepads/snespad/rtl/vhdl/snespad.vhd
#set_global_assignment -name VHDL_FILE rtl/board/zefant_xs3/zefant_xs3_av.vhd
set_global_assignment -name VHDL_FILE rtl/tech/generic/syn_ram-generic_tech-a.vhd
set_global_assignment -name VHDL_FILE rtl/tech/generic/syn_rom-av_bios-a.vhd
set_global_assignment -name VHDL_FILE rtl/tech/generic/t410_rom-struct-a.vhd
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_fifo_ctrl.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_dma_req.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_wb_if.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_sout.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_soc.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_sin.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_rst.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_rf.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_prc.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_out_fifo.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_int.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_dma_if.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_cra.v
#set_global_assignment -name VHDL_FILE rtl/board/misc/ac97_ctrl/rtl/verilog/ac97_top.v
set_global_assignment -name VHDL_FILE rtl/assets/rom_t41x.vhd
set_global_assignment -name VHDL_FILE rtl/assets/adventurevision_bios.vhd

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-- This file was generated with hex2rom written by Daniel Wallner
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity rom_t41x is
port(
Clk : in std_logic;
A : in std_logic_vector(8 downto 0);
D : out std_logic_vector(7 downto 0)
);
end rom_t41x;
architecture rtl of rom_t41x is
signal A_r : std_logic_vector(8 downto 0);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
A_r <= A;
end if;
end process;
process (A_r)
begin
case to_integer(unsigned(A_r)) is
when 000000 => D <= "00000000"; -- 0x0000
when 000001 => D <= "00001000"; -- 0x0001
when 000002 => D <= "00110011"; -- 0x0002
when 000003 => D <= "00101110"; -- 0x0003
when 000004 => D <= "01000100"; -- 0x0004
when 000005 => D <= "00000100"; -- 0x0005
when 000006 => D <= "00110011"; -- 0x0006
when 000007 => D <= "00101110"; -- 0x0007
when 000008 => D <= "00000100"; -- 0x0008
when 000009 => D <= "00000000"; -- 0x0009
when 000010 => D <= "01100001"; -- 0x000A
when 000011 => D <= "11110000"; -- 0x000B
when 000012 => D <= "00110010"; -- 0x000C
when 000013 => D <= "00111000"; -- 0x000D
when 000014 => D <= "00000101"; -- 0x000E
when 000015 => D <= "00110000"; -- 0x000F
when 000016 => D <= "01000100"; -- 0x0010
when 000017 => D <= "00000100"; -- 0x0011
when 000018 => D <= "00000101"; -- 0x0012
when 000019 => D <= "00110000"; -- 0x0013
when 000020 => D <= "01000100"; -- 0x0014
when 000021 => D <= "00000100"; -- 0x0015
when 000022 => D <= "00000101"; -- 0x0016
when 000023 => D <= "00110000"; -- 0x0017
when 000024 => D <= "01000100"; -- 0x0018
when 000025 => D <= "00000100"; -- 0x0019
when 000026 => D <= "00000101"; -- 0x001A
when 000027 => D <= "00110000"; -- 0x001B
when 000028 => D <= "01000100"; -- 0x001C
when 000029 => D <= "00000100"; -- 0x001D
when 000030 => D <= "00000101"; -- 0x001E
when 000031 => D <= "00110000"; -- 0x001F
when 000032 => D <= "01000100"; -- 0x0020
when 000033 => D <= "00000110"; -- 0x0021
when 000034 => D <= "00110011"; -- 0x0022
when 000035 => D <= "00111010"; -- 0x0023
when 000036 => D <= "00000000"; -- 0x0024
when 000037 => D <= "00010001"; -- 0x0025
when 000038 => D <= "01011000"; -- 0x0026
when 000039 => D <= "00111011"; -- 0x0027
when 000040 => D <= "00000011"; -- 0x0028
when 000041 => D <= "01011000"; -- 0x0029
when 000042 => D <= "01000100"; -- 0x002A
when 000043 => D <= "00111000"; -- 0x002B
when 000044 => D <= "01011000"; -- 0x002C
when 000045 => D <= "01011000"; -- 0x002D
when 000046 => D <= "01001101"; -- 0x002E
when 000047 => D <= "00111111"; -- 0x002F
when 000048 => D <= "00100001"; -- 0x0030
when 000049 => D <= "11110011"; -- 0x0031
when 000050 => D <= "01001000"; -- 0x0032
when 000051 => D <= "01010001"; -- 0x0033
when 000052 => D <= "11101111"; -- 0x0034
when 000053 => D <= "10110101"; -- 0x0035
when 000054 => D <= "00001110"; -- 0x0036
when 000055 => D <= "01110011"; -- 0x0037
when 000056 => D <= "11111100"; -- 0x0038
when 000057 => D <= "10110101"; -- 0x0039
when 000058 => D <= "00001110"; -- 0x003A
when 000059 => D <= "01111111"; -- 0x003B
when 000060 => D <= "00011110"; -- 0x003C
when 000061 => D <= "01111111"; -- 0x003D
when 000062 => D <= "00001110"; -- 0x003E
when 000063 => D <= "00000101"; -- 0x003F
when 000064 => D <= "00000110"; -- 0x0040
when 000065 => D <= "10000000"; -- 0x0041
when 000066 => D <= "00101111"; -- 0x0042
when 000067 => D <= "00010011"; -- 0x0043
when 000068 => D <= "11000111"; -- 0x0044
when 000069 => D <= "00001110"; -- 0x0045
when 000070 => D <= "10000000"; -- 0x0046
when 000071 => D <= "00001110"; -- 0x0047
when 000072 => D <= "00000101"; -- 0x0048
when 000073 => D <= "01011111"; -- 0x0049
when 000074 => D <= "11001100"; -- 0x004A
when 000075 => D <= "11000000"; -- 0x004B
when 000076 => D <= "10011011"; -- 0x004C
when 000077 => D <= "11001101"; -- 0x004D
when 000078 => D <= "01100001"; -- 0x004E
when 000079 => D <= "11110000"; -- 0x004F
when 000080 => D <= "10110101"; -- 0x0050
when 000081 => D <= "00001110"; -- 0x0051
when 000082 => D <= "01110000"; -- 0x0052
when 000083 => D <= "00011110"; -- 0x0053
when 000084 => D <= "01111111"; -- 0x0054
when 000085 => D <= "00001110"; -- 0x0055
when 000086 => D <= "00000101"; -- 0x0056
when 000087 => D <= "00000110"; -- 0x0057
when 000088 => D <= "10000000"; -- 0x0058
when 000089 => D <= "00101111"; -- 0x0059
when 000090 => D <= "00010011"; -- 0x005A
when 000091 => D <= "11011110"; -- 0x005B
when 000092 => D <= "00001110"; -- 0x005C
when 000093 => D <= "10000000"; -- 0x005D
when 000094 => D <= "00001110"; -- 0x005E
when 000095 => D <= "00000101"; -- 0x005F
when 000096 => D <= "01010001"; -- 0x0060
when 000097 => D <= "11010111"; -- 0x0061
when 000098 => D <= "10011011"; -- 0x0062
when 000099 => D <= "11100011"; -- 0x0063
when 000100 => D <= "01100001"; -- 0x0064
when 000101 => D <= "11110000"; -- 0x0065
when 000102 => D <= "10110101"; -- 0x0066
when 000103 => D <= "00001110"; -- 0x0067
when 000104 => D <= "01111000"; -- 0x0068
when 000105 => D <= "11010011"; -- 0x0069
when 000106 => D <= "10110101"; -- 0x006A
when 000107 => D <= "00001110"; -- 0x006B
when 000108 => D <= "01111101"; -- 0x006C
when 000109 => D <= "11010011"; -- 0x006D
when 000110 => D <= "00000000"; -- 0x006E
when 000111 => D <= "00000000"; -- 0x006F
when 000112 => D <= "00000000"; -- 0x0070
when 000113 => D <= "00000000"; -- 0x0071
when 000114 => D <= "00000000"; -- 0x0072
when 000115 => D <= "00000000"; -- 0x0073
when 000116 => D <= "00000000"; -- 0x0074
when 000117 => D <= "00000000"; -- 0x0075
when 000118 => D <= "00000000"; -- 0x0076
when 000119 => D <= "00000000"; -- 0x0077
when 000120 => D <= "00000000"; -- 0x0078
when 000121 => D <= "00000000"; -- 0x0079
when 000122 => D <= "00000000"; -- 0x007A
when 000123 => D <= "00000000"; -- 0x007B
when 000124 => D <= "00000000"; -- 0x007C
when 000125 => D <= "00000000"; -- 0x007D
when 000126 => D <= "00000000"; -- 0x007E
when 000127 => D <= "00000000"; -- 0x007F
when 000128 => D <= "00010101"; -- 0x0080
when 000129 => D <= "01010001"; -- 0x0081
when 000130 => D <= "10000001"; -- 0x0082
when 000131 => D <= "00000101"; -- 0x0083
when 000132 => D <= "00110011"; -- 0x0084
when 000133 => D <= "00111010"; -- 0x0085
when 000134 => D <= "01011111"; -- 0x0086
when 000135 => D <= "10001010"; -- 0x0087
when 000136 => D <= "00010110"; -- 0x0088
when 000137 => D <= "10000000"; -- 0x0089
when 000138 => D <= "00000110"; -- 0x008A
when 000139 => D <= "01001000"; -- 0x008B
when 000140 => D <= "00001010"; -- 0x008C
when 000141 => D <= "00001011"; -- 0x008D
when 000142 => D <= "00001100"; -- 0x008E
when 000143 => D <= "01001110"; -- 0x008F
when 000144 => D <= "00011000"; -- 0x0090
when 000145 => D <= "00100010"; -- 0x0091
when 000146 => D <= "00110000"; -- 0x0092
when 000147 => D <= "01000100"; -- 0x0093
when 000148 => D <= "00000100"; -- 0x0094
when 000149 => D <= "00000000"; -- 0x0095
when 000150 => D <= "01000000"; -- 0x0096
when 000151 => D <= "00110000"; -- 0x0097
when 000152 => D <= "01001001"; -- 0x0098
when 000153 => D <= "00000110"; -- 0x0099
when 000154 => D <= "01001000"; -- 0x009A
when 000155 => D <= "00101111"; -- 0x009B
when 000156 => D <= "00000001"; -- 0x009C
when 000157 => D <= "01001001"; -- 0x009D
when 000158 => D <= "01001000"; -- 0x009E
when 000159 => D <= "01101000"; -- 0x009F
when 000160 => D <= "10101101"; -- 0x00A0
when 000161 => D <= "01101001"; -- 0x00A1
when 000162 => D <= "11110100"; -- 0x00A2
when 000163 => D <= "00111111"; -- 0x00A3
when 000164 => D <= "01110000"; -- 0x00A4
when 000165 => D <= "01101000"; -- 0x00A5
when 000166 => D <= "00001100"; -- 0x00A6
when 000167 => D <= "10100101"; -- 0x00A7
when 000168 => D <= "00001001"; -- 0x00A8
when 000169 => D <= "00000101"; -- 0x00A9
when 000170 => D <= "00101111"; -- 0x00AA
when 000171 => D <= "00000110"; -- 0x00AB
when 000172 => D <= "10101100"; -- 0x00AC
when 000173 => D <= "00101111"; -- 0x00AD
when 000174 => D <= "00000011"; -- 0x00AE
when 000175 => D <= "00001111"; -- 0x00AF
when 000176 => D <= "00001110"; -- 0x00B0
when 000177 => D <= "00110011"; -- 0x00B1
when 000178 => D <= "00111110"; -- 0x00B2
when 000179 => D <= "00101000"; -- 0x00B3
when 000180 => D <= "01001000"; -- 0x00B4
when 000181 => D <= "00101111"; -- 0x00B5
when 000182 => D <= "00000011"; -- 0x00B6
when 000183 => D <= "00001111"; -- 0x00B7
when 000184 => D <= "00001110"; -- 0x00B8
when 000185 => D <= "00110011"; -- 0x00B9
when 000186 => D <= "00111110"; -- 0x00BA
when 000187 => D <= "01001000"; -- 0x00BB
when 000188 => D <= "00101111"; -- 0x00BC
when 000189 => D <= "00000000"; -- 0x00BD
when 000190 => D <= "00010011"; -- 0x00BE
when 000191 => D <= "01011011"; -- 0x00BF
when 000192 => D <= "01010111"; -- 0x00C0
when 000193 => D <= "01000100"; -- 0x00C1
when 000194 => D <= "00111110"; -- 0x00C2
when 000195 => D <= "00000110"; -- 0x00C3
when 000196 => D <= "01001000"; -- 0x00C4
when 000197 => D <= "00101111"; -- 0x00C5
when 000198 => D <= "00000000"; -- 0x00C6
when 000199 => D <= "00010011"; -- 0x00C7
when 000200 => D <= "01010101"; -- 0x00C8
when 000201 => D <= "01011111"; -- 0x00C9
when 000202 => D <= "01000100"; -- 0x00CA
when 000203 => D <= "00111110"; -- 0x00CB
when 000204 => D <= "00000110"; -- 0x00CC
when 000205 => D <= "01001000"; -- 0x00CD
when 000206 => D <= "00000000"; -- 0x00CE
when 000207 => D <= "00000000"; -- 0x00CF
when 000208 => D <= "00000000"; -- 0x00D0
when 000209 => D <= "00000000"; -- 0x00D1
when 000210 => D <= "00000000"; -- 0x00D2
when 000211 => D <= "00000000"; -- 0x00D3
when 000212 => D <= "00000000"; -- 0x00D4
when 000213 => D <= "00000000"; -- 0x00D5
when 000214 => D <= "00000000"; -- 0x00D6
when 000215 => D <= "00000000"; -- 0x00D7
when 000216 => D <= "00000000"; -- 0x00D8
when 000217 => D <= "00000000"; -- 0x00D9
when 000218 => D <= "00000000"; -- 0x00DA
when 000219 => D <= "00000000"; -- 0x00DB
when 000220 => D <= "00000000"; -- 0x00DC
when 000221 => D <= "00000000"; -- 0x00DD
when 000222 => D <= "00000000"; -- 0x00DE
when 000223 => D <= "00000000"; -- 0x00DF
when 000224 => D <= "00000000"; -- 0x00E0
when 000225 => D <= "00000000"; -- 0x00E1
when 000226 => D <= "00000000"; -- 0x00E2
when 000227 => D <= "00000000"; -- 0x00E3
when 000228 => D <= "00000000"; -- 0x00E4
when 000229 => D <= "00000000"; -- 0x00E5
when 000230 => D <= "00000000"; -- 0x00E6
when 000231 => D <= "00000000"; -- 0x00E7
when 000232 => D <= "00000000"; -- 0x00E8
when 000233 => D <= "00000000"; -- 0x00E9
when 000234 => D <= "00000000"; -- 0x00EA
when 000235 => D <= "00000000"; -- 0x00EB
when 000236 => D <= "00000000"; -- 0x00EC
when 000237 => D <= "00000000"; -- 0x00ED
when 000238 => D <= "00000000"; -- 0x00EE
when 000239 => D <= "00000000"; -- 0x00EF
when 000240 => D <= "00000000"; -- 0x00F0
when 000241 => D <= "00000000"; -- 0x00F1
when 000242 => D <= "00000000"; -- 0x00F2
when 000243 => D <= "00000000"; -- 0x00F3
when 000244 => D <= "00000000"; -- 0x00F4
when 000245 => D <= "00000000"; -- 0x00F5
when 000246 => D <= "00000000"; -- 0x00F6
when 000247 => D <= "00000000"; -- 0x00F7
when 000248 => D <= "00000000"; -- 0x00F8
when 000249 => D <= "00000000"; -- 0x00F9
when 000250 => D <= "00000000"; -- 0x00FA
when 000251 => D <= "00000000"; -- 0x00FB
when 000252 => D <= "00000000"; -- 0x00FC
when 000253 => D <= "00000000"; -- 0x00FD
when 000254 => D <= "00000000"; -- 0x00FE
when 000255 => D <= "00000000"; -- 0x00FF
when 000256 => D <= "00010011"; -- 0x0100
when 000257 => D <= "00010101"; -- 0x0101
when 000258 => D <= "00010111"; -- 0x0102
when 000259 => D <= "00011001"; -- 0x0103
when 000260 => D <= "00011011"; -- 0x0104
when 000261 => D <= "00111001"; -- 0x0105
when 000262 => D <= "00110111"; -- 0x0106
when 000263 => D <= "00111110"; -- 0x0107
when 000264 => D <= "00111011"; -- 0x0108
when 000265 => D <= "00101110"; -- 0x0109
when 000266 => D <= "00110001"; -- 0x010A
when 000267 => D <= "01001001"; -- 0x010B
when 000268 => D <= "01000111"; -- 0x010C
when 000269 => D <= "01000101"; -- 0x010D
when 000270 => D <= "01000011"; -- 0x010E
when 000271 => D <= "01000001"; -- 0x010F
when 000272 => D <= "00001001"; -- 0x0110
when 000273 => D <= "00000000"; -- 0x0111
when 000274 => D <= "11111111"; -- 0x0112
when 000275 => D <= "01010101"; -- 0x0113
when 000276 => D <= "11011100"; -- 0x0114
when 000277 => D <= "01011000"; -- 0x0115
when 000278 => D <= "11011100"; -- 0x0116
when 000279 => D <= "01011011"; -- 0x0117
when 000280 => D <= "11011100"; -- 0x0118
when 000281 => D <= "01011110"; -- 0x0119
when 000282 => D <= "11011100"; -- 0x011A
when 000283 => D <= "11011110"; -- 0x011B
when 000284 => D <= "01010001"; -- 0x011C
when 000285 => D <= "11011100"; -- 0x011D
when 000286 => D <= "10001100"; -- 0x011E
when 000287 => D <= "11100001"; -- 0x011F
when 000288 => D <= "01001000"; -- 0x0120
when 000289 => D <= "00000000"; -- 0x0121
when 000290 => D <= "01010010"; -- 0x0122
when 000291 => D <= "01000100"; -- 0x0123
when 000292 => D <= "01000100"; -- 0x0124
when 000293 => D <= "01010001"; -- 0x0125
when 000294 => D <= "11100011"; -- 0x0126
when 000295 => D <= "00011111"; -- 0x0127
when 000296 => D <= "00000101"; -- 0x0128
when 000297 => D <= "01000000"; -- 0x0129
when 000298 => D <= "00000110"; -- 0x012A
when 000299 => D <= "00110011"; -- 0x012B
when 000300 => D <= "00111010"; -- 0x012C
when 000301 => D <= "11010000"; -- 0x012D
when 000302 => D <= "01011111"; -- 0x012E
when 000303 => D <= "01010001"; -- 0x012F
when 000304 => D <= "11101111"; -- 0x0130
when 000305 => D <= "10001101"; -- 0x0131
when 000306 => D <= "11110100"; -- 0x0132
when 000307 => D <= "01001000"; -- 0x0133
when 000308 => D <= "00000000"; -- 0x0134
when 000309 => D <= "01011000"; -- 0x0135
when 000310 => D <= "11100011"; -- 0x0136
when 000311 => D <= "01011010"; -- 0x0137
when 000312 => D <= "11111100"; -- 0x0138
when 000313 => D <= "01011000"; -- 0x0139
when 000314 => D <= "11111100"; -- 0x013A
when 000315 => D <= "01011110"; -- 0x013B
when 000316 => D <= "01100001"; -- 0x013C
when 000317 => D <= "00101111"; -- 0x013D
when 000318 => D <= "01011101"; -- 0x013E
when 000319 => D <= "01100001"; -- 0x013F
when 000320 => D <= "00111100"; -- 0x0140
when 000321 => D <= "01011011"; -- 0x0141
when 000322 => D <= "11001011"; -- 0x0142
when 000323 => D <= "01011010"; -- 0x0143
when 000324 => D <= "11001011"; -- 0x0144
when 000325 => D <= "01011001"; -- 0x0145
when 000326 => D <= "11001011"; -- 0x0146
when 000327 => D <= "01011000"; -- 0x0147
when 000328 => D <= "11001011"; -- 0x0148
when 000329 => D <= "01010111"; -- 0x0149
when 000330 => D <= "11001011"; -- 0x014A
when 000331 => D <= "01000100"; -- 0x014B
when 000332 => D <= "01000100"; -- 0x014C
when 000333 => D <= "01000100"; -- 0x014D
when 000334 => D <= "01010001"; -- 0x014E
when 000335 => D <= "11001101"; -- 0x014F
when 000336 => D <= "10001110"; -- 0x0150
when 000337 => D <= "01100001"; -- 0x0151
when 000338 => D <= "00100111"; -- 0x0152
when 000339 => D <= "01001000"; -- 0x0153
when 000340 => D <= "00101111"; -- 0x0154
when 000341 => D <= "00010001"; -- 0x0155
when 000342 => D <= "11011001"; -- 0x0156
when 000343 => D <= "00101111"; -- 0x0157
when 000344 => D <= "00000011"; -- 0x0158
when 000345 => D <= "00001111"; -- 0x0159
when 000346 => D <= "00001110"; -- 0x015A
when 000347 => D <= "00110011"; -- 0x015B
when 000348 => D <= "00111110"; -- 0x015C
when 000349 => D <= "00101111"; -- 0x015D
when 000350 => D <= "00000000"; -- 0x015E
when 000351 => D <= "00010011"; -- 0x015F
when 000352 => D <= "01010111"; -- 0x0160
when 000353 => D <= "01011111"; -- 0x0161
when 000354 => D <= "01000100"; -- 0x0162
when 000355 => D <= "00011001"; -- 0x0163
when 000356 => D <= "00000110"; -- 0x0164
when 000357 => D <= "01100001"; -- 0x0165
when 000358 => D <= "00010000"; -- 0x0166
when 000359 => D <= "01100000"; -- 0x0167
when 000360 => D <= "00111001"; -- 0x0168
when 000361 => D <= "01100000"; -- 0x0169
when 000362 => D <= "01100110"; -- 0x016A
when 000363 => D <= "00000101"; -- 0x016B
when 000364 => D <= "01011111"; -- 0x016C
when 000365 => D <= "11110000"; -- 0x016D
when 000366 => D <= "00000110"; -- 0x016E
when 000367 => D <= "01001000"; -- 0x016F
when 000368 => D <= "00000111"; -- 0x0170
when 000369 => D <= "00000101"; -- 0x0171
when 000370 => D <= "01011111"; -- 0x0172
when 000371 => D <= "01001001"; -- 0x0173
when 000372 => D <= "11101110"; -- 0x0174
when 000373 => D <= "01100000"; -- 0x0175
when 000374 => D <= "00110101"; -- 0x0176
when 000375 => D <= "01100000"; -- 0x0177
when 000376 => D <= "01101010"; -- 0x0178
when 000377 => D <= "01100000"; -- 0x0179
when 000378 => D <= "01010000"; -- 0x017A
when 000379 => D <= "00101000"; -- 0x017B
when 000380 => D <= "01110010"; -- 0x017C
when 000381 => D <= "00001111"; -- 0x017D
when 000382 => D <= "00110011"; -- 0x017E
when 000383 => D <= "00111110"; -- 0x017F
when 000384 => D <= "01100001"; -- 0x0180
when 000385 => D <= "10001100"; -- 0x0181
when 000386 => D <= "01101000"; -- 0x0182
when 000387 => D <= "10101101"; -- 0x0183
when 000388 => D <= "01110001"; -- 0x0184
when 000389 => D <= "00111111"; -- 0x0185
when 000390 => D <= "01111100"; -- 0x0186
when 000391 => D <= "01100001"; -- 0x0187
when 000392 => D <= "10001110"; -- 0x0188
when 000393 => D <= "01101000"; -- 0x0189
when 000394 => D <= "10101101"; -- 0x018A
when 000395 => D <= "01110000"; -- 0x018B
when 000396 => D <= "00111111"; -- 0x018C
when 000397 => D <= "01110000"; -- 0x018D
when 000398 => D <= "01101001"; -- 0x018E
when 000399 => D <= "11110100"; -- 0x018F
when 000400 => D <= "01101000"; -- 0x0190
when 000401 => D <= "11000101"; -- 0x0191
when 000402 => D <= "01101000"; -- 0x0192
when 000403 => D <= "00001100"; -- 0x0193
when 000404 => D <= "00111101"; -- 0x0194
when 000405 => D <= "00000101"; -- 0x0195
when 000406 => D <= "01011111"; -- 0x0196
when 000407 => D <= "11011010"; -- 0x0197
when 000408 => D <= "00000110"; -- 0x0198
when 000409 => D <= "11010010"; -- 0x0199
when 000410 => D <= "00000100"; -- 0x019A
when 000411 => D <= "00000101"; -- 0x019B
when 000412 => D <= "01011111"; -- 0x019C
when 000413 => D <= "01010001"; -- 0x019D
when 000414 => D <= "11011000"; -- 0x019E
when 000415 => D <= "01101000"; -- 0x019F
when 000416 => D <= "10111100"; -- 0x01A0
when 000417 => D <= "00101000"; -- 0x01A1
when 000418 => D <= "00000001"; -- 0x01A2
when 000419 => D <= "11101110"; -- 0x01A3
when 000420 => D <= "00010001"; -- 0x01A4
when 000421 => D <= "11110101"; -- 0x01A5
when 000422 => D <= "00111111"; -- 0x01A6
when 000423 => D <= "00000101"; -- 0x01A7
when 000424 => D <= "01010001"; -- 0x01A8
when 000425 => D <= "11110010"; -- 0x01A9
when 000426 => D <= "10011011"; -- 0x01AA
when 000427 => D <= "11101011"; -- 0x01AB
when 000428 => D <= "01100001"; -- 0x01AC
when 000429 => D <= "11110000"; -- 0x01AD
when 000430 => D <= "00111111"; -- 0x01AE
when 000431 => D <= "00000101"; -- 0x01AF
when 000432 => D <= "01011111"; -- 0x01B0
when 000433 => D <= "11101010"; -- 0x01B1
when 000434 => D <= "00000110"; -- 0x01B2
when 000435 => D <= "01100001"; -- 0x01B3
when 000436 => D <= "10010010"; -- 0x01B4
when 000437 => D <= "00111111"; -- 0x01B5
when 000438 => D <= "00010011"; -- 0x01B6
when 000439 => D <= "11111010"; -- 0x01B7
when 000440 => D <= "01111010"; -- 0x01B8
when 000441 => D <= "11100110"; -- 0x01B9
when 000442 => D <= "00001110"; -- 0x01BA
when 000443 => D <= "00110011"; -- 0x01BB
when 000444 => D <= "00111110"; -- 0x01BC
when 000445 => D <= "11100110"; -- 0x01BD
when 000446 => D <= "00110010"; -- 0x01BE
when 000447 => D <= "11000001"; -- 0x01BF
when 000448 => D <= "00100010"; -- 0x01C0
when 000449 => D <= "00000000"; -- 0x01C1
when 000450 => D <= "01010001"; -- 0x01C2
when 000451 => D <= "00110000"; -- 0x01C3
when 000452 => D <= "01000100"; -- 0x01C4
when 000453 => D <= "00000111"; -- 0x01C5
when 000454 => D <= "00000000"; -- 0x01C6
when 000455 => D <= "00110000"; -- 0x01C7
when 000456 => D <= "01000100"; -- 0x01C8
when 000457 => D <= "00000111"; -- 0x01C9
when 000458 => D <= "00000000"; -- 0x01CA
when 000459 => D <= "00110000"; -- 0x01CB
when 000460 => D <= "11001110"; -- 0x01CC
when 000461 => D <= "01001000"; -- 0x01CD
when 000462 => D <= "00000110"; -- 0x01CE
when 000463 => D <= "01001001"; -- 0x01CF
when 000464 => D <= "01100000"; -- 0x01D0
when 000465 => D <= "10011111"; -- 0x01D1
when 000466 => D <= "01101001"; -- 0x01D2
when 000467 => D <= "01010100"; -- 0x01D3
when 000468 => D <= "01101001"; -- 0x01D4
when 000469 => D <= "01010111"; -- 0x01D5
when 000470 => D <= "01101001"; -- 0x01D6
when 000471 => D <= "01010111"; -- 0x01D7
when 000472 => D <= "10011011"; -- 0x01D8
when 000473 => D <= "11011001"; -- 0x01D9
when 000474 => D <= "11010010"; -- 0x01DA
when 000475 => D <= "00000000"; -- 0x01DB
when 000476 => D <= "00000000"; -- 0x01DC
when 000477 => D <= "00000000"; -- 0x01DD
when 000478 => D <= "00000000"; -- 0x01DE
when 000479 => D <= "00000000"; -- 0x01DF
when 000480 => D <= "11111011"; -- 0x01E0
when 000481 => D <= "11010000"; -- 0x01E1
when 000482 => D <= "01100111"; -- 0x01E2
when 000483 => D <= "01111011"; -- 0x01E3
when 000484 => D <= "01111001"; -- 0x01E4
when 000485 => D <= "10000010"; -- 0x01E5
when 000486 => D <= "10001001"; -- 0x01E6
when 000487 => D <= "01110101"; -- 0x01E7
when 000488 => D <= "01110111"; -- 0x01E8
when 000489 => D <= "01101001"; -- 0x01E9
when 000490 => D <= "01101011"; -- 0x01EA
when 000491 => D <= "01101011"; -- 0x01EB
when 000492 => D <= "01101011"; -- 0x01EC
when 000493 => D <= "01101011"; -- 0x01ED
when 000494 => D <= "11010010"; -- 0x01EE
when 000495 => D <= "11010010"; -- 0x01EF
when 000496 => D <= "00001000"; -- 0x01F0
when 000497 => D <= "00000000"; -- 0x01F1
when 000498 => D <= "01011110"; -- 0x01F2
when 000499 => D <= "11111111"; -- 0x01F3
when 000500 => D <= "00111000"; -- 0x01F4
when 000501 => D <= "01110000"; -- 0x01F5
when 000502 => D <= "01110000"; -- 0x01F6
when 000503 => D <= "01110000"; -- 0x01F7
when 000504 => D <= "01110000"; -- 0x01F8
when 000505 => D <= "01110111"; -- 0x01F9
when 000506 => D <= "01001000"; -- 0x01FA
when 000507 => D <= "01100000"; -- 0x01FB
when 000508 => D <= "10101000"; -- 0x01FC
when 000509 => D <= "00000000"; -- 0x01FD
when 000510 => D <= "00000000"; -- 0x01FE
when others => D <= "--------";
end case;
end process;
end;

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-------------------------------------------------------------------------------
--
-- FPGA Adventure Vision
--
-- $Id: av_comp_pack-p.vhd,v 1.12 2006/05/06 23:40:56 arnim Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package av_comp_pack is
component av_main
port (
-- System Interface -----------------------------------------------------
clk_11m_i : in std_logic;
reset_n_i : in std_logic;
por_n_o : out std_logic;
-- Cartridge Interface --------------------------------------------------
cart_a_o : out std_logic_vector(11 downto 0);
cart_oe_n_o : out std_logic;
cart_d_i : in std_logic_vector( 7 downto 0);
-- Controller Interface -------------------------------------------------
ctrl_i : in std_logic_vector( 7 downto 3);
-- Sound Interface ------------------------------------------------------
snd_res_n_o : out std_logic;
snd_p2_o : out std_logic_vector( 7 downto 4);
-- Display Interface ----------------------------------------------------
disp_d_o : out std_logic_vector( 7 downto 0);
disp_p24_n_o : out std_logic;
disp_rd_n_o : out std_logic;
disp_p2_o : out std_logic_vector( 7 downto 5);
disp_reset_clk_i : in std_logic;
disp_photo_int_i : in std_logic;
-- Expansion Interface --------------------------------------------------
exp_t0_i : in std_logic;
exp_t0_o : out std_logic;
exp_t0_dir_o : out std_logic;
exp_rd_n_o : out std_logic;
exp_psen_n_o : out std_logic;
exp_wr_n_o : out std_logic;
exp_ale_o : out std_logic;
exp_d_i : in std_logic_vector( 7 downto 0);
exp_d_o : out std_logic_vector( 7 downto 0);
exp_p1_i : in std_logic_vector( 7 downto 3);
exp_p1_o : out std_logic_vector( 7 downto 3);
exp_p1_low_imp_o : out std_logic;
exp_p2_i : in std_logic_vector( 3 downto 0);
exp_p2_o : out std_logic_vector( 3 downto 0);
exp_p2l_low_imp_o : out std_logic;
exp_p2h_low_imp_o : out std_logic;
exp_prog_n_o : out std_logic
);
end component;
component av_ctrl
port (
-- Control Interface ----------------------------------------------------
ctrl_o : out std_logic_vector(7 downto 3);
-- Buttons and Stick Interface ------------------------------------------
but_1_n_i : in std_logic;
but_2_n_i : in std_logic;
but_3_n_i : in std_logic;
but_4_n_i : in std_logic;
stick_l_n_i : in std_logic;
stick_r_n_i : in std_logic;
stick_u_n_i : in std_logic;
stick_d_n_i : in std_logic;
-- Sound Interface ------------------------------------------------------
clk_11m_i : in std_logic;
por_n_i : in std_logic;
snd_res_n_i : in std_logic;
snd_p2_i : in std_logic_vector(7 downto 4);
audio_o : out std_logic_vector(1 downto 0)
);
end component;
component av_disp
port (
-- System Interface -----------------------------------------------------
clk_11m_i : in std_logic;
por_n_i : in std_logic;
-- Display Interface ----------------------------------------------------
disp_d_i : in std_logic_vector( 7 downto 0);
disp_p24_n_i : in std_logic;
disp_rd_n_i : in std_logic;
disp_p2_i : in std_logic_vector( 7 downto 5);
disp_reset_clk_o : out std_logic;
disp_photo_int_o : out std_logic;
-- LED Interface --------------------------------------------------------
led_n_o : out std_logic_vector(39 downto 0)
);
end component;
end av_comp_pack;

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-------------------------------------------------------------------------------
--
-- FPGA Adventure Vision
--
-- $Id: av_ctrl.vhd,v 1.7 2006/05/09 21:11:29 arnim Exp $
--
-- Controller PCB
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity av_ctrl is
port (
-- Control Interface ------------------------------------------------------
ctrl_o : out std_logic_vector(7 downto 3);
-- Buttons and Stick Interface --------------------------------------------
but_1_n_i : in std_logic;
but_2_n_i : in std_logic;
but_3_n_i : in std_logic;
but_4_n_i : in std_logic;
stick_l_n_i : in std_logic;
stick_r_n_i : in std_logic;
stick_u_n_i : in std_logic;
stick_d_n_i : in std_logic;
-- Sound Interface --------------------------------------------------------
clk_11m_i : in std_logic;
por_n_i : in std_logic;
snd_res_n_i : in std_logic;
snd_p2_i : in std_logic_vector(7 downto 4);
audio_o : out std_logic_vector(1 downto 0)
);
end av_ctrl;
library ieee;
use ieee.numeric_std.all;
use work.t400_opt_pack.all;
use work.t400_system_comp_pack.t410_notri;
architecture rtl of av_ctrl is
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s,
io_g_s : std_logic_vector(3 downto 0);
signal clk_842k_en_s : std_logic;
signal clk_842k_cnt_q : unsigned(3 downto 0);
signal gnd4_s : std_logic_vector(3 downto 0);
begin
gnd4_s <= (others => '0');
-----------------------------------------------------------------------------
-- COP411L sound controller
-----------------------------------------------------------------------------
io_l_s(7 downto 4) <= (others => '0');
io_l_s(3 downto 0) <= snd_p2_i;
--
cop411_b : t410_notri
generic map (
opt_ck_div_g => t400_opt_ck_div_16_c
)
port map (
ck_i => clk_11m_i,
ck_en_i => clk_842k_en_s,
reset_n_i => snd_res_n_i,
cko_i => gnd4_s(0),
io_l_i => io_l_s,
io_l_o => open,
io_l_en_o => open,
io_d_o => io_d_s,
io_d_en_o => open,
io_g_i => gnd4_s,
io_g_o => io_g_s,
io_g_en_o => open,
si_i => gnd4_s(0),
so_o => open,
so_en_o => open,
sk_o => open,
sk_en_o => open
);
--
audio_o(1) <= io_d_s(0); -- 0 = high, 1 = low volume
audio_o(0) <= io_g_s(0); -- digital sound waveform
-----------------------------------------------------------------------------
-- Process clk_842
--
-- Purpose:
-- Generates the 842 kHz clock for the COP411L.
--
clk_842: process (clk_11m_i, por_n_i)
begin
if por_n_i = '0' then
clk_842k_cnt_q <= to_unsigned(12, 4);
elsif clk_11m_i'event and clk_11m_i = '1' then
if clk_842k_en_s = '1' then
clk_842k_cnt_q <= to_unsigned(12, 4);
else
clk_842k_cnt_q <= clk_842k_cnt_q - 1;
end if;
end if;
end process clk_842;
--
clk_842k_en_s <= '1'
when clk_842k_cnt_q = 0 else
'0';
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process ctrl
--
-- Purpose:
-- Encodes the button and stick inputs to the control bus.
--
ctrl: process (but_1_n_i, but_2_n_i, but_3_n_i, but_4_n_i,
stick_l_n_i, stick_r_n_i, stick_u_n_i, stick_d_n_i)
variable ctrl_v : std_logic_vector(7 downto 3);
begin
ctrl_v := (others => '1');
if but_1_n_i = '0' then
ctrl_v(5) := '0';
ctrl_v(4) := '0';
end if;
if but_2_n_i = '0' then
ctrl_v(6) := '0';
ctrl_v(4) := '0';
end if;
if but_3_n_i = '0' then
ctrl_v(3) := '0';
end if;
if but_4_n_i = '0' then
ctrl_v(7) := '0';
ctrl_v(4) := '0';
end if;
-- priority encoder required here
-- joystick is only 4-way, positions NW, NE, SW and SE do not exist
if stick_l_n_i = '0' then
ctrl_v(7) := '0';
elsif stick_r_n_i = '0' then
ctrl_v(6) := '0';
elsif stick_u_n_i = '0' then
ctrl_v(5) := '0';
elsif stick_d_n_i = '0' then
ctrl_v(4) := '0';
end if;
ctrl_o <= ctrl_v;
end process ctrl;
--
-----------------------------------------------------------------------------
end rtl;

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-------------------------------------------------------------------------------
--
-- FPGA Adventure Vision
--
-- $Id: av_disp.vhd,v 1.9 2006/04/02 18:37:59 arnim Exp $
--
-- Display PCB
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity av_disp is
port (
-- System Interface -------------------------------------------------------
clk_11m_i : in std_logic;
por_n_i : in std_logic;
-- Display Interface ------------------------------------------------------
disp_d_i : in std_logic_vector( 7 downto 0);
disp_p24_n_i : in std_logic;
disp_rd_n_i : in std_logic;
disp_p2_i : in std_logic_vector( 7 downto 5);
disp_reset_clk_o : out std_logic;
disp_photo_int_o : out std_logic;
-- LED Interface ----------------------------------------------------------
led_n_o : out std_logic_vector(39 downto 0)
);
end av_disp;
library ieee;
use ieee.numeric_std.all;
architecture rtl of av_disp is
constant mirror_cnt_width_c : natural := 24;
-- interruptor closed time: 200 us
constant interruptor_reload_c : natural := 2220;
-- mirror rotation time from : 66.67 ms - interruptor closed time
constant mirror_rot_reload_c : natural := 739918 -
interruptor_reload_c;
signal mirror_cnt_q : unsigned(mirror_cnt_width_c-1 downto 0);
signal interruptor_closed_q : std_logic;
signal disp_photo_int_s : std_logic;
signal led_pre_n_q,
led_n_q : std_logic_vector(39 downto 0);
signal p24_n_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process mirror
--
-- Purpose:
-- Implements the counter that emulates the rotating mirror.
--
mirror: process (clk_11m_i, por_n_i)
begin
if por_n_i = '0' then
mirror_cnt_q <= to_unsigned(mirror_rot_reload_c,
mirror_cnt_width_c);
interruptor_closed_q <= '0';
elsif clk_11m_i'event and clk_11m_i = '1' then
if mirror_cnt_q = 0 then
if interruptor_closed_q = '0' then
-- mirror moved to position where interruptor will be closed
-- time closing phase
mirror_cnt_q <= to_unsigned(interruptor_reload_c,
mirror_cnt_width_c);
else
-- mirror moved out of interruptor
mirror_cnt_q <= to_unsigned(mirror_rot_reload_c,
mirror_cnt_width_c);
end if;
-- flip interruptor
interruptor_closed_q <= not interruptor_closed_q;
else
mirror_cnt_q <= mirror_cnt_q - 1;
end if;
end if;
end process mirror;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process leds
--
-- Purpose:
-- Implements the registers for saving the LED data.
-- Data is stored in two steps:
-- a) sequential write to led_pre_q
-- b) full parallel update to led_q
--
-- Note that the LED signals are active low. I.e. LEDs are lit when control
-- signals are pulled to GND.
--
leds: process (clk_11m_i, por_n_i)
begin
if por_n_i = '0' then
led_pre_n_q <= (others => '1');
led_n_q <= (others => '1');
p24_n_q <= '0';
elsif clk_11m_i'event and clk_11m_i = '1' then
p24_n_q <= disp_p24_n_i;
-- latch while /RD is active
if disp_rd_n_i = '0'then
case disp_p2_i is
when "001" =>
led_pre_n_q( 7 downto 0) <= disp_d_i;
when "010" =>
led_pre_n_q(15 downto 8) <= disp_d_i;
when "011" =>
led_pre_n_q(23 downto 16) <= disp_d_i;
when "100" =>
led_pre_n_q(31 downto 24) <= disp_d_i;
when "101" =>
led_pre_n_q(39 downto 32) <= disp_d_i;
when others =>
null;
end case;
end if;
if interruptor_closed_q = '0' then
-- detect falling edge on /P2.4
if disp_p24_n_i = '0' and p24_n_q = '1' then
-- update LEDs
led_n_q <= led_pre_n_q;
end if;
else
-- clear LEDs
-- required for Super Cobra
led_n_q <= (others => '1');
end if;
end if;
end process leds;
--
disp_photo_int_s <= not interruptor_closed_q;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
disp_photo_int_o <= disp_photo_int_s;
led_n_o <= led_n_q;
-- propagate /RD to reset flip-flop clock when P2 is set to C
disp_reset_clk_o <= disp_rd_n_i
when disp_p2_i = "110" else
'1';
end rtl;

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-------------------------------------------------------------------------------
--
-- FPGA Adventure Vision
--
-- $Id: av_machine.vhd,v 1.6 2006/05/06 23:40:56 arnim Exp $
--
-- Toplevel of the Adventure Vision console
--
-- References:
--
-- * AdventureVision.com
-- The comprehensive source of information
--
-- * Dan Boris' technical resources of the Adventure Vision
-- http://www.atarihq.com/danb/adventurevision.shtml
--
-- * PCB Schematics, same source
-- http://www.atarihq.com/danb/files/AvSchematic.pdf
--
-- * Technical manual, same source
-- http://www.atarihq.com/danb/files/AvTechSpecs.pdf
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity av_machine is
port (
-- System Interface -------------------------------------------------------
clk_11m_i : in std_logic;
reset_n_i : in std_logic;
por_n_o : out std_logic;
-- Cartridge Interface ----------------------------------------------------
cart_a_o : out std_logic_vector(11 downto 0);
cart_oe_n_o : out std_logic;
cart_d_i : in std_logic_vector( 7 downto 0);
-- Buttons and Stick Interface --------------------------------------------
but_1_n_i : in std_logic;
but_2_n_i : in std_logic;
but_3_n_i : in std_logic;
but_4_n_i : in std_logic;
stick_l_n_i : in std_logic;
stick_r_n_i : in std_logic;
stick_u_n_i : in std_logic;
stick_d_n_i : in std_logic;
-- Sound Interface --------------------------------------------------------
audio_o : out std_logic_vector( 1 downto 0);
-- Display Interface ------------------------------------------------------
led_n_o : out std_logic_vector(39 downto 0);
disp_p24_n_o : out std_logic;
disp_photo_int_o : out std_logic;
-- Expansion Interface ----------------------------------------------------
exp_t0_i : in std_logic;
exp_t0_o : out std_logic;
exp_t0_dir_o : out std_logic;
exp_rd_n_o : out std_logic;
exp_psen_n_o : out std_logic;
exp_wr_n_o : out std_logic;
exp_ale_o : out std_logic;
exp_d_i : in std_logic_vector( 7 downto 0);
exp_d_o : out std_logic_vector( 7 downto 0);
exp_p1_i : in std_logic_vector( 7 downto 3);
exp_p1_o : out std_logic_vector( 7 downto 3);
exp_p1_low_imp_o : out std_logic;
exp_p2_i : in std_logic_vector( 3 downto 0);
exp_p2_o : out std_logic_vector( 3 downto 0);
exp_p2l_low_imp_o : out std_logic;
exp_p2h_low_imp_o : out std_logic;
exp_prog_n_o : out std_logic
);
end av_machine;
use work.av_comp_pack.av_main;
use work.av_comp_pack.av_ctrl;
use work.av_comp_pack.av_disp;
architecture struct of av_machine is
-- System connections
signal por_n_s : std_logic;
-- Control connections
signal ctrl_s : std_logic_vector(7 downto 3);
-- Sound connections
signal snd_res_n_s : std_logic;
signal snd_p2_s : std_logic_vector(7 downto 4);
-- Display connections
signal disp_d_s : std_logic_vector(7 downto 0);
signal disp_p24_n_s : std_logic;
signal disp_rd_n_s : std_logic;
signal disp_p2_s : std_logic_vector(7 downto 5);
signal disp_reset_clk_s : std_logic;
signal disp_photo_int_s : std_logic;
begin
-----------------------------------------------------------------------------
-- Main PCB
-----------------------------------------------------------------------------
main_b : av_main
port map (
clk_11m_i => clk_11m_i,
reset_n_i => reset_n_i,
por_n_o => por_n_s,
cart_a_o => cart_a_o,
cart_oe_n_o => cart_oe_n_o,
cart_d_i => cart_d_i,
ctrl_i => ctrl_s,
snd_res_n_o => snd_res_n_s,
snd_p2_o => snd_p2_s,
disp_d_o => disp_d_s,
disp_p24_n_o => disp_p24_n_s,
disp_rd_n_o => disp_rd_n_s,
disp_p2_o => disp_p2_s,
disp_reset_clk_i => disp_reset_clk_s,
disp_photo_int_i => disp_photo_int_s,
exp_t0_i => exp_t0_i,
exp_t0_o => exp_t0_o,
exp_t0_dir_o => exp_t0_dir_o,
exp_rd_n_o => exp_rd_n_o,
exp_psen_n_o => exp_psen_n_o,
exp_wr_n_o => exp_wr_n_o,
exp_ale_o => exp_ale_o,
exp_d_i => exp_d_i,
exp_d_o => exp_d_o,
exp_p1_i => exp_p1_i,
exp_p1_o => exp_p1_o,
exp_p1_low_imp_o => exp_p1_low_imp_o,
exp_p2_i => exp_p2_i,
exp_p2_o => exp_p2_o,
exp_p2l_low_imp_o => exp_p2l_low_imp_o,
exp_p2h_low_imp_o => exp_p2h_low_imp_o,
exp_prog_n_o => exp_prog_n_o
);
-----------------------------------------------------------------------------
-- Controller PCB
-----------------------------------------------------------------------------
ctrl_b : av_ctrl
port map (
ctrl_o => ctrl_s,
but_1_n_i => but_1_n_i,
but_2_n_i => but_2_n_i,
but_3_n_i => but_3_n_i,
but_4_n_i => but_4_n_i,
stick_l_n_i => stick_l_n_i,
stick_r_n_i => stick_r_n_i,
stick_u_n_i => stick_u_n_i,
stick_d_n_i => stick_d_n_i,
clk_11m_i => clk_11m_i,
por_n_i => por_n_s,
snd_res_n_i => snd_res_n_s,
snd_p2_i => snd_p2_s,
audio_o => audio_o
);
-----------------------------------------------------------------------------
-- Display PCB
-----------------------------------------------------------------------------
disp_b : av_disp
port map (
clk_11m_i => clk_11m_i,
por_n_i => por_n_s,
disp_d_i => disp_d_s,
disp_p24_n_i => disp_p24_n_s,
disp_rd_n_i => disp_rd_n_s,
disp_p2_i => disp_p2_s,
disp_reset_clk_o => disp_reset_clk_s,
disp_photo_int_o => disp_photo_int_s,
led_n_o => led_n_o
);
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
por_n_o <= por_n_s;
disp_p24_n_o <= disp_p24_n_s;
disp_photo_int_o <= disp_photo_int_s;
end struct;

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-------------------------------------------------------------------------------
--
-- FPGA Adventure Vision
--
-- $Id: av_machine_comp_pack-p.vhd,v 1.5 2006/04/02 18:51:11 arnim Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package av_machine_comp_pack is
component av_machine
port (
-- System Interface -----------------------------------------------------
clk_11m_i : in std_logic;
reset_n_i : in std_logic;
por_n_o : out std_logic;
-- Cartridge Interface --------------------------------------------------
cart_a_o : out std_logic_vector(11 downto 0);
cart_oe_n_o : out std_logic;
cart_d_i : in std_logic_vector( 7 downto 0);
-- Buttons and Stick Interface ------------------------------------------
but_1_n_i : in std_logic;
but_2_n_i : in std_logic;
but_3_n_i : in std_logic;
but_4_n_i : in std_logic;
stick_l_n_i : in std_logic;
stick_r_n_i : in std_logic;
stick_u_n_i : in std_logic;
stick_d_n_i : in std_logic;
-- Sound Interface ------------------------------------------------------
audio_o : out std_logic_vector( 1 downto 0);
-- Display Interface ----------------------------------------------------
led_n_o : out std_logic_vector(39 downto 0);
disp_p24_n_o : out std_logic;
disp_photo_int_o : out std_logic;
-- Expansion Interface --------------------------------------------------
exp_t0_i : in std_logic;
exp_t0_o : out std_logic;
exp_t0_dir_o : out std_logic;
exp_rd_n_o : out std_logic;
exp_psen_n_o : out std_logic;
exp_wr_n_o : out std_logic;
exp_ale_o : out std_logic;
exp_d_i : in std_logic_vector( 7 downto 0);
exp_d_o : out std_logic_vector( 7 downto 0);
exp_p1_i : in std_logic_vector( 7 downto 3);
exp_p1_o : out std_logic_vector( 7 downto 3);
exp_p1_low_imp_o : out std_logic;
exp_p2_i : in std_logic_vector( 3 downto 0);
exp_p2_o : out std_logic_vector( 3 downto 0);
exp_p2l_low_imp_o : out std_logic;
exp_p2h_low_imp_o : out std_logic;
exp_prog_n_o : out std_logic
);
end component;
end av_machine_comp_pack;

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-------------------------------------------------------------------------------
--
-- FPGA Adventure Vision
--
-- $Id: av_main.vhd,v 1.14 2006/05/13 14:54:55 arnim Exp $
--
-- Main PCB
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity av_main is
port (
-- System Interface -------------------------------------------------------
clk_11m_i : in std_logic;
reset_n_i : in std_logic;
por_n_o : out std_logic;
-- Cartridge Interface ----------------------------------------------------
cart_a_o : out std_logic_vector(11 downto 0);
cart_oe_n_o : out std_logic;
cart_d_i : in std_logic_vector( 7 downto 0);
-- Controller Interface ---------------------------------------------------
ctrl_i : in std_logic_vector( 7 downto 3);
-- Sound Interface --------------------------------------------------------
snd_res_n_o : out std_logic;
snd_p2_o : out std_logic_vector( 7 downto 4);
-- Display Interface ------------------------------------------------------
disp_d_o : out std_logic_vector( 7 downto 0);
disp_p24_n_o : out std_logic;
disp_rd_n_o : out std_logic;
disp_p2_o : out std_logic_vector( 7 downto 5);
disp_reset_clk_i : in std_logic;
disp_photo_int_i : in std_logic;
-- Expansion Interface ----------------------------------------------------
exp_t0_i : in std_logic;
exp_t0_o : out std_logic;
exp_t0_dir_o : out std_logic;
exp_rd_n_o : out std_logic;
exp_psen_n_o : out std_logic;
exp_wr_n_o : out std_logic;
exp_ale_o : out std_logic;
exp_d_i : in std_logic_vector( 7 downto 0);
exp_d_o : out std_logic_vector( 7 downto 0);
exp_p1_i : in std_logic_vector( 7 downto 3);
exp_p1_o : out std_logic_vector( 7 downto 3);
exp_p1_low_imp_o : out std_logic;
exp_p2_i : in std_logic_vector( 3 downto 0);
exp_p2_o : out std_logic_vector( 3 downto 0);
exp_p2l_low_imp_o : out std_logic;
exp_p2h_low_imp_o : out std_logic;
exp_prog_n_o : out std_logic
);
end av_main;
use work.tech_comp_pack.av_por;
use work.t48_system_comp_pack.t8048_notri;
use work.tech_comp_pack.generic_ram;
architecture struct of av_main is
-- System connections
signal por_n_s : std_logic;
signal reset_n_s : std_logic;
signal a_q : std_logic_vector(7 downto 0);
-- T48 connections
signal ale_s : std_logic;
signal rd_n_s,
wr_n_s : std_logic;
signal psen_n_s : std_logic;
signal db_to_t48_s,
db_from_t48_s : std_logic_vector(7 downto 0);
signal db_dir_s : std_logic;
signal t1_s : std_logic;
signal p1_to_t48_s,
p1_from_t48_s : std_logic_vector(7 downto 0);
signal p2_to_t48_s,
p2_from_t48_s : std_logic_vector(7 downto 0);
-- RAM connections
signal ram_we_s : std_logic;
signal d_ram_s,
d_from_ram_s : std_logic_vector(7 downto 0);
signal ram_a_s : std_logic_vector(9 downto 0);
signal d_from_cart_s : std_logic_vector(7 downto 0);
signal disp_enable_s : std_logic;
signal db0_q : std_logic;
signal disp_reset_clk_q : std_logic;
signal snd_res_n_q : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Power-on reset circuit
-- Reset active for at most 28.5 ms.
-- The power-on reset time is calculated from the RC element present at
-- the reset pin of the 8048:
-- C = 1 uF, R = 20 kOhm (estimated from pin input leakage I_LI2)
-- V_IH = 3.8 V
-----------------------------------------------------------------------------
por_b : av_por
generic map (
delay_g => 6315,
cnt_width_g => 19
)
port map (
clk_i => clk_11m_i,
por_n_o => por_n_s
);
por_n_o <= por_n_s;
reset_n_s <= reset_n_i and por_n_s;
-----------------------------------------------------------------------------
-- T48 uController in 8048 flavour without tri-states
-----------------------------------------------------------------------------
t8048_notri_b : t8048_notri
generic map (
gate_port_input_g => 1
)
port map (
xtal_i => clk_11m_i,
reset_n_i => reset_n_s,
t0_i => exp_t0_i,
t0_o => exp_t0_o,
t0_dir_o => exp_t0_dir_o,
int_n_i => vdd_s,
ea_i => p1_from_t48_s(2),
rd_n_o => rd_n_s,
psen_n_o => psen_n_s,
wr_n_o => wr_n_s,
ale_o => ale_s,
db_i => db_to_t48_s,
db_o => db_from_t48_s,
db_dir_o => db_dir_s,
t1_i => t1_s,
p2_i => p2_to_t48_s,
p2_o => p2_from_t48_s,
p2l_low_imp_o => exp_p2l_low_imp_o,
p2h_low_imp_o => exp_p2h_low_imp_o,
p1_i => p1_to_t48_s,
p1_o => p1_from_t48_s,
p1_low_imp_o => exp_p1_low_imp_o,
prog_n_o => exp_prog_n_o
);
-- build DB input bus
db_to_t48_s <= d_from_ram_s and
d_from_cart_s and
exp_d_i;
-- set bus from cartridge to inactive when cartridge is not selected
d_from_cart_s <= cart_d_i
when psen_n_s = '0' else
(others => '1');
-- build P1 input bus
p1_to_t48_s(2 downto 0) <= (others => '1');
p1_to_t48_s(7 downto 3) <= ctrl_i and exp_p1_i;
-- build P2 input bus
p2_to_t48_s(3 downto 0) <= exp_p2_i;
p2_to_t48_s(7 downto 4) <= (others => '1');
t1_s <= not disp_photo_int_i;
-----------------------------------------------------------------------------
-- Process alatch
--
-- Purpose:
-- Implements the address latch.
--
alatch: process (clk_11m_i, por_n_s)
begin
if por_n_s = '0' then
a_q <= (others => '0');
elsif clk_11m_i'event and clk_11m_i = '1' then
if ale_s = '1' then
a_q <= db_from_t48_s;
end if;
end if;
end process alatch;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- External RAM
-----------------------------------------------------------------------------
ram_we_s <= not wr_n_s;
ram_a_s <= p1_from_t48_s(1) & p1_from_t48_s(0) &
a_q;
--
ext_ram_b : generic_ram
generic map (
addr_width_g => 10,
data_width_g => 8
)
port map (
clk_i => clk_11m_i,
a_i => ram_a_s,
we_i => ram_we_s,
d_i => db_from_t48_s,
d_o => d_ram_s
);
-- set bus from RAM to inactive state when RAM is not selected
d_from_ram_s <= d_ram_s
when rd_n_s = '0' else
(others => '1');
-----------------------------------------------------------------------------
-- Display disabled for at most 240 ms.
-- The disable time is calculated from the RC element present at
-- pin 2 of the 74LS00:
-- C = 47 uF, R = 10 kOhm
-- V_IH = 2 V
-----------------------------------------------------------------------------
disp_en_b : av_por
generic map (
delay_g => 3706,
cnt_width_g => 26
)
port map (
clk_i => clk_11m_i,
por_n_o => disp_enable_s
);
-----------------------------------------------------------------------------
-- Process db_reg
--
-- Purpose:
-- Saves DB(0) when DB is written to by MOVX.
--
db_reg: process (clk_11m_i, por_n_s)
begin
if por_n_s = '0' then
db0_q <= '0';
elsif clk_11m_i'event and clk_11m_i = '1' then
if wr_n_s = '0' then
db0_q <= db_from_t48_s(0);
end if;
end if;
end process db_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process snd_res
--
-- Purpose:
-- Implements the flip-flop for resetting the COP411L sound controller.
--
snd_res: process (clk_11m_i, por_n_s)
begin
if por_n_s = '0' then
disp_reset_clk_q <= '0';
snd_res_n_q <= '0';
elsif clk_11m_i'event and clk_11m_i = '1' then
disp_reset_clk_q <= disp_reset_clk_i;
if disp_reset_clk_i = '1' and disp_reset_clk_q = '0' then
snd_res_n_q <= db0_q;
end if;
end if;
end process snd_res;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
-- Sound Interface
snd_res_n_o <= snd_res_n_q;
snd_p2_o <= p2_from_t48_s(7 downto 4);
-- Cartridge Interface
cart_a_o <= p2_from_t48_s(3) & p2_from_t48_s(2) &
p2_from_t48_s(1) & p2_from_t48_s(0) &
a_q;
cart_oe_n_o <= psen_n_s;
-- Display Interface
disp_d_o <= db_to_t48_s;
disp_p24_n_o <= disp_enable_s nand p2_from_t48_s(4);
disp_rd_n_o <= rd_n_s;
disp_p2_o <= p2_from_t48_s(7 downto 5);
-- Expansion Interface
exp_rd_n_o <= rd_n_s;
exp_psen_n_o <= psen_n_s;
exp_wr_n_o <= wr_n_s;
exp_ale_o <= ale_s;
exp_d_o <= db_from_t48_s;
exp_p1_o <= p1_from_t48_s(7 downto 3);
exp_p2_o <= p2_from_t48_s(3 downto 0);
end struct;

337
rtl/pll.qip Normal file
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@@ -0,0 +1,337 @@
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTEuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::NDQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjAw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NDQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::NDQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::LTYwLjA=::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTEuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::NDQuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MjIsMjIsMywyLGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsMjAsMjAsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsNSw1LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDIsMjAsMTAwMDAsNDQwLjAgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"]
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim"

255
rtl/pll.v Normal file
View File

@@ -0,0 +1,255 @@
// megafunction wizard: %Altera PLL v17.0%
// GENERATION: XML
// pll.v
// Generated using ACDS version 17.0 602
`timescale 1 ps / 1 ps
module pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
pll_0002 pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2022 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="true" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="11.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="44.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="-60.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="20.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="10.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll.vo
// RELATED_FILES: pll.v, pll_0002.v

4
rtl/pll/pll_0002.qip Normal file
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set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"

90
rtl/pll/pll_0002.v Normal file
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`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("11.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("44.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

4
rtl/pll/pll_0002_q13.qip Normal file
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@@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"

19
rtl/t400/CHANGELOG Normal file
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@@ -0,0 +1,19 @@
Change log for the T400 uController core
========================================
Version: $Date: 2006/06/12 18:12:57 $
Release 1.0
-----------
* Production test plus related testbench added.
* Bugfix for
"Timer skipped in T421 configuration"
* T421 system and testbench added.
* T410 system and testbench added.
* Regression test suite environment enhanced for T421 system.

92
rtl/t400/COMPILE_LIST Normal file
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rtl/vhdl/t400_opt_pack-p.vhd
rtl/vhdl/t400_clkgen.vhd
rtl/vhdl/t400_clkgen-c.vhd
rtl/vhdl/t400_reset.vhd
rtl/vhdl/t400_reset-c.vhd
rtl/vhdl/t400_pack-p.vhd
bench/vhdl/tb_pack-p.vhd
rtl/vhdl/t400_pmem_ctrl.vhd
rtl/vhdl/t400_pmem_ctrl-c.vhd
rtl/vhdl/t400_dmem_ctrl.vhd
rtl/vhdl/t400_dmem_ctrl-c.vhd
rtl/vhdl/t400_opc_table.vhd
rtl/vhdl/t400_opc_table-c.vhd
rtl/vhdl/t400_comp_pack-p.vhd
rtl/vhdl/t400_decoder.vhd
rtl/vhdl/t400_decoder-c.vhd
rtl/vhdl/t400_skip.vhd
rtl/vhdl/t400_skip-c.vhd
rtl/vhdl/t400_alu.vhd
rtl/vhdl/t400_alu-c.vhd
rtl/vhdl/t400_stack.vhd
rtl/vhdl/t400_stack-c.vhd
rtl/vhdl/t400_io_pack-p.vhd
rtl/vhdl/t400_io_l.vhd
rtl/vhdl/t400_io_l-c.vhd
rtl/vhdl/t400_io_d.vhd
rtl/vhdl/t400_io_d-c.vhd
rtl/vhdl/t400_io_g.vhd
rtl/vhdl/t400_io_g-c.vhd
rtl/vhdl/t400_io_in.vhd
rtl/vhdl/t400_io_in-c.vhd
rtl/vhdl/t400_sio.vhd
rtl/vhdl/t400_sio-c.vhd
rtl/vhdl/t400_timer.vhd
rtl/vhdl/t400_timer-c.vhd
rtl/vhdl/t400_core.vhd
rtl/vhdl/t400_core-c.vhd
rtl/tech/generic/generic_ram_ena.vhd
rtl/tech/generic/generic_ram_ena-c.vhd
bench/vhdl/lpm_rom.vhd
rtl/vhdl/system/t410_rom-e.vhd
bench/vhdl/t410_rom-lpm-a.vhd
bench/vhdl/t410_rom-lpm-c.vhd
rtl/tech/cyclone/t400_por.vhd
rtl/tech/cyclone/t400_por-c.vhd
rtl/vhdl/t400_core_comp_pack-p.vhd
rtl/tech/t400_tech_comp_pack-p.vhd
rtl/vhdl/system/t410_notri.vhd
rtl/vhdl/system/t410_notri-c.vhd
rtl/vhdl/system/t400_system_comp_pack-p.vhd
rtl/vhdl/system/t410.vhd
rtl/vhdl/system/t410-c.vhd
bench/vhdl/tb_elems.vhd
bench/vhdl/tb_elems-c.vhd
bench/vhdl/tb_t410.vhd
bench/vhdl/tb_t410-c.vhd
Elaborate toplevel tb_t410_behav_c0.
rtl/vhdl/system/t411.vhd
rtl/vhdl/system/t411-c.vhd
bench/vhdl/tb_t411.vhd
bench/vhdl/tb_t411-c.vhd
Elaborate toplevel tb_t411_behav_c0.
rtl/vhdl/system/t420_rom-e.vhd
bench/vhdl/t420_rom-lpm-a.vhd
bench/vhdl/t420_rom-lpm-c.vhd
rtl/vhdl/system/t420_notri.vhd
rtl/vhdl/system/t420_notri-c.vhd
rtl/vhdl/system/t420.vhd
rtl/vhdl/system/t420-c.vhd
bench/vhdl/tb_t420.vhd
bench/vhdl/tb_t420-c.vhd
Elaborate toplevel tb_t420_behav_c0.
rtl/vhdl/system/t421.vhd
rtl/vhdl/system/t421-c.vhd
bench/vhdl/tb_t421.vhd
bench/vhdl/tb_t421-c.vhd
Elaborate toplevel tb_t421_behav_c0.
bench/vhdl/tb_int.vhd
bench/vhdl/tb_int-c.vhd
Elaborate toplevel tb_int_behav_c0.
bench/vhdl/tb_microbus.vhd
bench/vhdl/tb_microbus-c.vhd
Elaborate toplevel tb_microbus_behav_c0.
bench/vhdl/tb_prod.vhd
bench/vhdl/tb_prod-c.vhd
Elaborate toplevel tb_prod_behav_c0.

340
rtl/t400/COPYING Normal file
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@@ -0,0 +1,340 @@
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
the GNU Library General Public License instead.) You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
this service if you wish), that you receive source code or can get it
if you want it, that you can change the software or use pieces of it
in new free programs; and that you know you can do these things.
To protect your rights, we need to make restrictions that forbid
anyone to deny you these rights or to ask you to surrender the rights.
These restrictions translate to certain responsibilities for you if you
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8. If the distribution and/or use of the Program is restricted in
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may add an explicit geographical distribution limitation excluding
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9. The Free Software Foundation may publish revised and/or new versions
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Each version is given a distinguishing version number. If the Program
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10. If you wish to incorporate parts of the Program into other free
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NO WARRANTY
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END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) 19yy <name of author>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) 19yy name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Library General
Public License instead of this License.

19
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Known bugs of the T400 uController core
=======================================
Version: $Date: 2006/06/12 18:12:57 $
Release 0.1 BETA
----------------
*******************************************************************************
Timer skipped in T421 configuration
When the generic opt_type_g is set to t400_opt_type_421_c inside t400_core,
the timer module is not included in the core. This is wrong because the COP421
chip contains this timer.
Fixed in:
t400_core.vhd 1.10
Fix will be included in next release.

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README for the T400 uController project
=======================================
Version: $Date: 2006/06/12 18:12:57 $
Introduction
------------
The T400 µController core is an implementation of the COP400 microcontroller
family architecture. <more text from webpage>
Download
--------
Download the latest stable release from the project homepage at OpenCores.org:
http://www.opencores.org/projects.cgi/web/t400/overview/
You can get the latest version of the design files from CVS:
http://www.opencores.org/pdownloads.cgi/list/t400
Please keep in mind that this is work in progress and might contain smaller or
bigger problems.
You should also check the Tracker for known bugs and see if they affect your
work.
Installation
------------
Once the directory structure is generated either by check-out from CVS or by
unpacking the tar-archive, the central project initialization file should be
set up. A template called init_project.template.sh is located in the sw
directory where a copy can be edited. Normally, only the definition for the
variable PROJECT_DIR has to be adjusted to the path where the directory
structure is located.
The commands for setting the necessary variables assume a bash/sh-like
shell. In case you run a different shell like csh or ksh, you should adjust
these commands as well.
The meaning of the variables is as follows:
* PROJECT_DIR
Points to the root of the project installation. All further references are
derived from its setting.
* MAKEFILES
Identifies the global Makefile for compilation of tests.
These variables must be properly set whenever scripts or makefiles of the T400
project are executed that are related to verification tasks. Otherwise, you
will most likely encounter error messages.
NOTE: The concepts of the mentioned shells require that the init_project.sh is
run in the context of the shell. I.e. you should 'source' the script
instead of executing it like a command. This will make sure that the
variable settings are really effective in the calling shell instance.
Directory Structure
-------------------
The project's directory structure follows the proposal of OpenCores.org.
t400
|
\--+-- rtl
| |
| +-- vhdl : VHDL code containing the RTL description
| | | of the core.
| | \-- system : RTL VHDL code of sample systems.
| |
| \-- tech : Technology specific files.
| |
| +-- cyclone : Cyclone technology flavor.
| |
| +-- spartan : Spartan technology flavor.
| |
| \-- generic : Generic RTL designs.
|
+-- bench
| |
| \-- vhdl : VHDL testbench code.
|
+-- sim
| |
| \-- rtl_sim : Directory for running simulations.
|
\-- sw : General purpose scripts and files.
|
\-- verif : The verification suite.
|
+-- include : Global includes and makefiles.
|
+-- black_box : Black-box verification tests.
|
+-- int : Interrupt verification tests.
|
\-- system : General system level tests.
Compiling the VHDL Code
-----------------------
VHDL compilation and simulation tasks take place inside in sim/rtl_sim
directory. The project setup supports only the batch mode of certain
simulators. However, there should be no problems to integrate the testbench
and RTL code into arbitrary simulation environments.
The main file for compilation is Makefile which contains all information
regarding the dependencies of the source files and their compilation
order.
Compilation is based on the make-utility, thus invocation looks like this:
$ make
This will call ghdl to analzye and elaborate the complete design hierarchy.
Tristan Gingold's GHDL simulator/compiler, a VHDL front-end for gcc.
http://ghdl.free.fr/
Make will analyze all VHDL files (RTL and testbench code) and elaborate all
testbench top-levels:
* tb_t410_behav_c0
Testbench for the T410 derivative.
It instantiates the T410 system toplevel and is intended to exectue all
verifcation tests tagged with 't41x'.
* tb_t411_behav_c0
Testbench for the T411 derivative.
It instantiates the T411 system toplevel and is intended to exectue all
verifcation tests tagged with 't41x'.
* tb_t420_behav_c0
The testbench for the T420 derivative.
It instantiates the T420 system toplevel and is intended to execute all
verification tests tagged with 't42x' and 't420'.
* tb_t421_behav_c0
The testbench for the T421 derivative.
It instantiates the T421 system toplevel and is intended to execute all
verification tests tagged with 't42x'.
* tb_int_behav_c0
The testbench for the interrupt verification suite.
It instantiates the T420 system topevel and is intended to execute all
verification tests tagged with 'int'.
* tb_microbus_behav_c0
The testbench for the microbus verification.
It instantiates the T420 system toplevel in microbus configuration and is
intended to execute all verifications tests tagged with 'mb'.
* tb_prod_behav_c0
The testbench for the production test.
It instantiates the T420 system toplevel an checks D and P output ports
for the patterns generated by the software as proposed in
"Testing of COP400 Familiy Devices"
National Semiconductor
COP Note 7
April 1991
The Makefile has a 'clean' target to delete all intermediate data:
$ make clean
The basic simple sequence list can be found in COMPILE_LIST. This can be
useful to quickly set up the analyze stage of any compiler or
synthesizer. Especially when synthesizing the code, you want to skip the VHDL
configurations in *-c.vhd and everything below the bench/ directory.
Preparation of the ROM Files
----------------------------
All testbenches listed above load the internal ROM of the controller from a
file in hex-format. Its existance is mandatory as it is referenced in the
VHDL code of the ROM model lpm_rom.vhd. In case it is missing, the
simulation will stop immediately after elaborating the design.
These files are:
* rom_41x.hex
Program ROM compiled for the T41x derivatives. Maximum size 512 bytes.
Referenced by the t410_notri system.
Enabled by the 't41x' tag.
* rom_42x.hex
Program ROM compiled for the T42x derivatives. Maximum size 1024 bytes.
Referenced by the t420_notri system.
Enabled by the 't42x', 't420', 'int', 'mb' and 'prod' tag.
The verification flow for the T400 project generates these two files
automatically from the assembler source files. Whenever the make process
locates one or more of the above tags, it assembles and links the source code
for the repsective derivative.
All regression tests and the general purpose software is organized in a cell
structure. Currently, this means that the software for a cell is contained in
a dedicated directory where the assembler run takes place. In the future,
there will be more aspects to a cell.
Assembling, linking and putting the hex-files in place is under the control of
the make-mechanism. E.g. to assemble the source code of a cell, issue the
following command:
$ make
The above mention environment variable MAKEFILES enables execution of the make
process from within any subdirectory in the verification tree. This generates
the linker file (test_41x.p and test_42x.p) and derives hex-files which are
placed into the simulation directory. So most likely, for running a test case
or any other software, you will want to issue:
The only supported assembler is Alfred Arnold's macroassembler AS. See
http://john.ccac.rwth-aachen.de:8000/as/
Verification Environment
------------------------
The verification environment consists of a number of test programs. They are
all self-checking. I.e. after testing the targeted functionality, they emit a
pass/fail information. This information is detected by the testbench which
stops the simulation and prints out the simulation result. This is the default
mechanism for stopping the VHDL simulation.
Pass/fail is signalled by a certain sequence of the L port contents:
(R denotes an optional value stored in A when calling the pass or fail
routines)
1) L outputs 0x0R
2) L outputs 0xaR
3) L outputs 0x5R
4) L outputs 0x0R -> Pass
L outputs 0xfR -> Fail
The detection is modelled like a state machine and in case the sequence is of
bytes inside the accumulator does not match, the detection process restarts
from the beginning. This mechanism is part of all verification tests except
for the interrupt testbench.
The complete regression suite can be executed with the run_regression.pl
script. For each test cell, it steps through the sequence
1) Assemble the source code
2) Run the compiled VHDL design (currently only GHDL)
It is highly recommended to redirect the output of run_regression.pl into a
file. Otherwise, analyzing the messages related to each test cell is almost
impossible.
Clocking System
---------------
The main clock is supplied at input ck_i. To ease system integration, ck_i can
accept integer multiples of the target clock frequency. Input ck_en_i is used
to qualify rising edges on ck_i as active clock edges. When ck_i is supplied
with the target frequency, ck_en_i can be kept high constantly.
Generic Parameters
------------------
Most generic parameters are provided to set the numerous I/O options. Thus
such options are exhibited on the toplevel designs.
All generics are implemented with integer types to enable analysis of the RTL
code without tool restrictions. The related constants are defined in
t400_opt_pack-p.vhd.
opt_type_g : Derivative type - T420, T421, T410, T411
opt_ck_div_g : Internal divider on CK
opt_cko_g : Enable CKO as general purpose input
opt_l_out_type_7_g : Output driver type L[7]
opt_l_out_type_6_g : Output driver type L[6]
opt_l_out_type_5_g : Output driver type L[5]
opt_l_out_type_4_g : Output driver type L[4]
opt_l_out_type_3_g : Output driver type L[3]
opt_l_out_type_2_g : Output driver type L[2]
opt_l_out_type_1_g : Output driver type L[1]
opt_l_out_type_0_g : Output driver type L[0]
opt_microbus_g : Enable MICROBUS interface
opt_d_out_type_3_g : Output driver type D[3]
opt_d_out_type_2_g : Output driver type D[2]
opt_d_out_type_1_g : Output driver type D[1]
opt_d_out_type_0_g : Output driver type D[0]
opt_g_out_type_3_g : Output driver type G[3]
opt_g_out_type_2_g : Output driver type G[2]
opt_g_out_type_1_g : Output driver type G[1]
opt_g_out_type_0_g : Output driver type G[0]
opt_so_output_type_g : Output driver type SO
opt_sk_output_type_g : Output driver type SK
FPGA Implementation
-------------------
All of the design files contain pure RTL code. This is true even for the
technology specific power-on reset module. Two flavors exist, each of them
implementing the desired behavior in a way that is understood by the design
tools. The RAM for the data memory is described by generic RTL code as
well. It should be translated automatically by the tool chain to a technology
specific RAM macro.
There is a generic method for the program memory ROM as well, although this
project uses a flow where hex-files are loaded by lpm_rom.vhd as the default
method. Convert the ROM image to an RTL VHDL file with one of the two
following commands (either from hex or bin format):
$ hex2rom -b [rom image file] rom_t41x 9l8s > rom_t41x.vhd
$ hex2rom -b [rom image file] rom_t42x 10l8s > rom_t42x.vhd
The option -b specifies that <rom image file> contains binary data. Skip this
option to process a file in hex format.
These resulting RTL representations are instantiated by t410_rom-struct-a.vhd
and t420_rom-struct-a.vhd. Altera and Xilinx design tools will detect and
extract the ROM and turn it into a memory macro.

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-------------------------------------------------------------------------------
--
-- $Id: tb_pack-p.vhd,v 1.1.1.1 2006/06/10 18:06:11 arnim Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.pc_t;
package tb_pack is
component tb_elems
generic (
period_g : time := 4.75 us;
d_width_g : integer := 4;
g_width_g : integer := 4
);
port (
io_l_i : in std_logic_vector(7 downto 0);
io_d_i : in std_logic_vector(d_width_g-1 downto 0);
io_g_i : in std_logic_vector(g_width_g-1 downto 0);
io_in_o : out std_logic_vector(g_width_g-1 downto 0);
so_i : in std_logic;
si_o : out std_logic;
sk_i : in std_logic;
ck_o : out std_logic
);
end component;
signal tb_pc_s : pc_t;
signal tb_sa_s : pc_t;
end tb_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: tb_pack-p.vhd,v $
-- Revision 1.1.1.1 2006/06/10 18:06:11 arnim
-- copied from opencores.org repository, pre-1.0 release on 10-Jun-2006
--
-- Revision 1.3 2006/05/27 19:09:29 arniml
-- add global signals for testbench instrumentation
--
-- Revision 1.2 2006/05/23 01:17:25 arniml
-- drive IN port
--
-- Revision 1.1 2006/05/15 21:55:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

23
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-------------------------------------------------------------------------------
-- $Id: t400_por-c.vhd,v 1.2 2006/05/07 01:49:16 arniml Exp $
-------------------------------------------------------------------------------
configuration t400_por_rtl_c0 of t400_por is
for cyclone
end for;
end t400_por_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_por-c.vhd,v $
-- Revision 1.2 2006/05/07 01:49:16 arniml
-- renamed to rtl
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T400 Core
--
-- $Id: t400_por.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Wrapper for technology dependent power-on reset circuitry.
--
-- Altera Cyclone flavor.
--
-- Generate a reset upon power-on for specified number of clocks.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t400_por is
generic (
delay_g : integer := 4;
cnt_width_g : integer := 2
);
port (
clk_i : in std_logic;
por_n_o : out std_logic
);
end t400_por;
library ieee;
use ieee.numeric_std.all;
architecture cyclone of t400_por is
signal por_cnt_q : unsigned(cnt_width_g-1 downto 0)
-- pragma translate_off
-- initialize for simulation only
:= (others => '0')
-- pragma translate_on
;
signal por_n_q : std_logic
-- pragma translate_off
-- initialize for simulation only
:= '0'
-- pragma translate_on
;
-- Specify power-up level of por counter and por source.
-- Refer to "Quartus II Integrated Synthesis", section "Altera Attribute".
attribute altera_attribute : string;
attribute altera_attribute of por_cnt_q : signal is "-name POWER_UP_LEVEL LOW";
attribute altera_attribute of por_n_q : signal is "-name POWER_UP_LEVEL LOW";
begin
-----------------------------------------------------------------------------
-- Process por_cnt
--
-- Purpose:
-- Generate a power-on reset for the specifiec number of clocks.
--
por_cnt: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if por_cnt_q = delay_g-1 then
por_n_q <= '1';
else
por_cnt_q <= por_cnt_q + 1;
end if;
end if;
end process por_cnt;
--
-----------------------------------------------------------------------------
por_n_o <= por_n_q;
end cyclone;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_por.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM.
--
-- $Id: generic_ram-c.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration generic_ram_rtl_c0 of generic_ram is
for rtl
end for;
end generic_ram_rtl_c0;

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-------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM.
--
-- $Id: generic_ram.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity generic_ram is
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end generic_ram;
library ieee;
use ieee.numeric_std.all;
architecture rtl of generic_ram is
type mem_t is array (natural range 0 to 2**addr_width_g-1) of
std_logic_vector(d_i'range);
signal mem_q : mem_t
-- pragma translate_off
:= (others => (others => '0'))
-- pragma translate_on
;
begin
mem: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if we_i = '1' then
mem_q(to_integer(unsigned(a_i))) <= d_i;
end if;
d_o <= mem_q(to_integer(unsigned(a_i)));
end if;
end process mem;
end rtl;

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-------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM with enable.
--
-- $Id: generic_ram_ena-c.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration generic_ram_ena_rtl_c0 of generic_ram_ena is
for rtl
end for;
end generic_ram_ena_rtl_c0;

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-------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM with enable.
--
-- $Id: generic_ram_ena.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity generic_ram_ena is
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
ena_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end generic_ram_ena;
library ieee;
use ieee.numeric_std.all;
architecture rtl of generic_ram_ena is
type mem_t is array (natural range 0 to 2**addr_width_g-1) of
std_logic_vector(d_i'range);
signal mem_q : mem_t
-- pragma translate_off
:= (others => (others => '0'))
-- pragma translate_on
;
begin
mem: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if ena_i = '1' then
if we_i = '1' then
mem_q(to_integer(unsigned(a_i))) <= d_i;
end if;
d_o <= mem_q(to_integer(unsigned(a_i)));
end if;
end if;
end process mem;
end rtl;

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-------------------------------------------------------------------------------
-- $Id: t400_por-c.vhd,v 1.1 2006/05/07 01:47:51 arniml Exp $
-------------------------------------------------------------------------------
configuration t400_por_rtl_c0 of t400_por is
for spartan
end for;
end t400_por_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_por-c.vhd,v $
-- Revision 1.1 2006/05/07 01:47:51 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T400 Core
--
-- $Id: t400_por.vhd,v 1.1 2006/05/07 01:47:51 arniml Exp $
--
-- Wrapper for technology dependent power-on reset circuitry.
--
-- Xilinx Spartan3 flavor.
--
-- Generate a reset upon power-on for specified number of clocks.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t400_por is
generic (
delay_g : integer := 4;
cnt_width_g : integer := 2
);
port (
clk_i : in std_logic;
por_n_o : out std_logic
);
end t400_por;
library ieee;
use ieee.numeric_std.all;
architecture spartan of t400_por is
-----------------------------------------------------------------------------
-- According to
-- "XST User Guide", Chapter 6 "VHDL Language Support", "Initial Values"
-- XST honors the initial value assigned to a flip-flop. Simple :-)
--
signal por_cnt_q : unsigned(cnt_width_g-1 downto 0)
:= to_unsigned(delay_g, cnt_width_g);
signal por_n_q : std_logic := '0';
--
-----------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------
-- Process por_cnt
--
-- Purpose:
-- Generate a power-on reset for the specified number of clocks.
--
por_cnt: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if por_cnt_q = 0 then
por_n_q <= '1';
else
por_cnt_q <= por_cnt_q - 1;
end if;
end if;
end process por_cnt;
--
-----------------------------------------------------------------------------
por_n_o <= por_n_q;
end spartan;

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-------------------------------------------------------------------------------
--
-- $Id: t400_tech_comp_pack-p.vhd,v 1.2 2006/06/05 20:31:00 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package t400_tech_comp_pack is
component t400_por
generic (
delay_g : integer := 4;
cnt_width_g : integer := 2
);
port (
clk_i : in std_logic;
por_n_o : out std_logic
);
end component;
component generic_ram
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end component;
component generic_ram_ena
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
ena_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end component;
end t400_tech_comp_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_tech_comp_pack-p.vhd,v $
-- Revision 1.2 2006/06/05 20:31:00 arniml
-- generic_ram_ena added
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- $Id: t400_system_comp_pack-p.vhd,v 1.6 2006/06/11 22:18:52 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
package t400_system_comp_pack is
component t410_notri
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end component;
component t410
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end component;
component t411
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(1 downto 0);
io_g_b : inout std_logic_vector(2 downto 0)
);
end component;
component t420_notri
generic (
opt_type_g : integer := t400_opt_type_420_c;
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end component;
component t420
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end component;
component t421
generic (
opt_ck_div_g : integer := t400_opt_ck_div_8_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end component;
end t400_system_comp_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_system_comp_pack-p.vhd,v $
-- Revision 1.6 2006/06/11 22:18:52 arniml
-- added t410
--
-- Revision 1.5 2006/06/11 13:48:13 arniml
-- * t421 added
-- * fixed generic list for t420 and t420_notri
--
-- Revision 1.4 2006/06/05 20:02:46 arniml
-- use microbus generic
--
-- Revision 1.3 2006/05/23 01:16:19 arniml
-- routi CKO to t400_core
--
-- Revision 1.2 2006/05/14 22:29:33 arniml
-- t420 hierarchies added
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T410 system toplevel.
--
-- $Id: t410-c.vhd,v 1.1.1.1 2006/06/12 18:12:58 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
configuration t410_struct_c0 of t410 is
for struct
for t410_notri_b: t410_notri
use configuration work.t410_notri_struct_c0;
end for;
end for;
end t410_struct_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t410-c.vhd,v $
-- Revision 1.1.1.1 2006/06/12 18:12:58 arnim
-- copied from opencores.org repository, 1.0 release
--
-- Revision 1.1 2006/06/11 22:18:28 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T410 system toplevel.
--
-- $Id: t410.vhd,v 1.1.1.1 2006/06/12 18:12:58 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t410 is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end t410;
use work.t400_system_comp_pack.t410_notri;
architecture struct of t410 is
signal io_l_from_t410_s,
io_l_en_s : std_logic_vector(7 downto 0);
signal io_d_from_t410_s,
io_d_en_s : std_logic_vector(3 downto 0);
signal io_g_to_t410_s,
io_g_from_t410_s,
io_g_en_s : std_logic_vector(3 downto 0);
signal so_s,
so_en_s : std_logic;
signal sk_s,
sk_en_s : std_logic;
signal gnd_s : std_logic;
begin
gnd_s <= '0';
-----------------------------------------------------------------------------
-- T410 without tri-states
-----------------------------------------------------------------------------
t410_notri_b : t410_notri
generic map (
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => t400_opt_cko_crystal_c,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
reset_n_i => reset_n_i,
cko_i => gnd_s,
io_l_i => io_l_b,
io_l_o => io_l_from_t410_s,
io_l_en_o => io_l_en_s,
io_d_o => io_d_from_t410_s,
io_d_en_o => io_d_en_s,
io_g_i => io_g_b,
io_g_o => io_g_from_t410_s,
io_g_en_o => io_g_en_s,
si_i => si_i,
so_o => so_s,
so_en_o => so_en_s,
sk_o => sk_s,
sk_en_o => sk_en_s
);
-----------------------------------------------------------------------------
-- Tri-states for output drivers
-----------------------------------------------------------------------------
io_l_tri: for idx in 7 downto 0 generate
io_l_b(idx) <= io_l_from_t410_s(idx)
when io_l_en_s(idx) = '1' else
'Z';
end generate;
--
io_d_tri: for idx in 3 downto 0 generate
io_d_o(idx) <= io_d_from_t410_s(idx)
when io_d_en_s(idx) = '1' else
'Z';
end generate;
--
io_g_tri: for idx in 3 downto 0 generate
io_g_b(idx) <= io_g_from_t410_s(idx)
when io_g_en_s(idx) = '1' else
'Z';
end generate;
--
so_o <= so_s
when so_en_s = '1' else
'Z';
--
sk_o <= sk_s
when sk_en_s = '1' else
'Z';
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t410.vhd,v $
-- Revision 1.1.1.1 2006/06/12 18:12:58 arnim
-- copied from opencores.org repository, 1.0 release
--
-- Revision 1.1 2006/06/11 22:18:28 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T410/411 controller toplevel without tri-states.
--
-- $Id: t410_notri-c.vhd,v 1.3 2006/06/05 20:03:11 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t410_notri_struct_c0 of t410_notri is
for struct
for core_b: t400_core
use configuration work.t400_core_struct_c0;
end for;
for pmem_b: t410_rom
use configuration work.t410_rom_struct_c0;
end for;
for dmem_b: generic_ram_ena
use configuration work.generic_ram_ena_rtl_c0;
end for;
for por_b: t400_por
use configuration work.t400_por_rtl_c0;
end for;
end for;
end t410_notri_struct_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t410_notri-c.vhd,v $
-- Revision 1.3 2006/06/05 20:03:11 arniml
-- include generic_ram_ena
--
-- Revision 1.2 2006/05/07 01:49:03 arniml
-- renamed t400_por configuration to rtl
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T410/411 controller toplevel without tri-states.
--
-- $Id: t410_notri.vhd,v 1.3 2006/06/05 20:03:11 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t410_notri is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end t410_notri;
use work.t400_core_comp_pack.t400_core;
use work.t400_tech_comp_pack.t400_por;
use work.t400_tech_comp_pack.generic_ram_ena;
architecture struct of t410_notri is
component t410_rom
port (
ck_i : in std_logic;
addr_i : in std_logic_vector(8 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end component;
signal por_n_s : std_logic;
signal pm_addr_s : std_logic_vector(9 downto 0);
signal pm_data_s : std_logic_vector(7 downto 0);
signal dm_addr_s : std_logic_vector(5 downto 0);
signal dm_we_s : std_logic;
signal dm_data_to_core_s,
dm_data_from_core_s : std_logic_vector(3 downto 0);
signal gnd4_s : std_logic_vector(3 downto 0);
begin
gnd4_s <= (others => '0');
-----------------------------------------------------------------------------
-- T400 core
-----------------------------------------------------------------------------
core_b : t400_core
generic map (
opt_type_g => t400_opt_type_410_c,
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => opt_cko_g,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => t400_opt_no_microbus_c,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
por_n_i => por_n_s,
reset_n_i => reset_n_i,
cko_i => cko_i,
pm_addr_o => pm_addr_s,
pm_data_i => pm_data_s,
dm_addr_o => dm_addr_s,
dm_we_o => dm_we_s,
dm_data_o => dm_data_from_core_s,
dm_data_i => dm_data_to_core_s,
io_l_i => io_l_i,
io_l_o => io_l_o,
io_l_en_o => io_l_en_o,
io_d_o => io_d_o,
io_d_en_o => io_d_en_o,
io_g_i => io_g_i,
io_g_o => io_g_o,
io_g_en_o => io_g_en_o,
io_in_i => gnd4_s,
si_i => si_i,
so_o => so_o,
so_en_o => so_en_o,
sk_o => sk_o,
sk_en_o => sk_en_o
);
-----------------------------------------------------------------------------
-- Program memory
-----------------------------------------------------------------------------
pmem_b : t410_rom
port map (
ck_i => ck_i,
addr_i => pm_addr_s(8 downto 0),
data_o => pm_data_s
);
-----------------------------------------------------------------------------
-- Data memory
-----------------------------------------------------------------------------
dmem_b : generic_ram_ena
generic map (
addr_width_g => 5,
data_width_g => 4
)
port map (
clk_i => ck_i,
a_i => dm_addr_s(4 downto 0),
we_i => dm_we_s,
ena_i => ck_en_i,
d_i => dm_data_from_core_s,
d_o => dm_data_to_core_s
);
-----------------------------------------------------------------------------
-- Power-on reset circuit
-----------------------------------------------------------------------------
por_b : t400_por
generic map (
delay_g => 4,
cnt_width_g => 2
)
port map (
clk_i => ck_i,
por_n_o => por_n_s
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t410_notri.vhd,v $
-- Revision 1.3 2006/06/05 20:03:11 arniml
-- include generic_ram_ena
--
-- Revision 1.2 2006/05/08 02:36:38 arniml
-- hand-down clock divider option
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T410/411 ROM.
--
-- $Id: t410_rom-e.vhd,v 1.1.1.1 2006/05/06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t410_rom is
port (
ck_i : in std_logic;
addr_i : in std_logic_vector(8 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end t410_rom;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t410_rom-e.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T410/411 ROM.
--
-- $Id: t410_rom-struct-a.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
architecture struct of t410_rom is
component rom_t41x
port(
Clk : in std_logic;
A : in std_logic_vector(8 downto 0);
D : out std_logic_vector(7 downto 0)
);
end component;
begin
rom_b : rom_t41x
port map (
Clk => ck_i,
A => addr_i,
D => data_o
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t410_rom-struct-a.vhd,v $
-- Revision 1.1.1.1 2006/06/10 17:50:15 arnim
-- copied from opencores.org repository, pre-1.0 release on 10-Jun-2006
--
-- Revision 1.1 2006/06/05 22:44:29 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T411 system toplevel.
--
-- $Id: t411-c.vhd,v 1.1.1.1 2006/05/06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
configuration t411_struct_c0 of t411 is
for struct
for t410_notri_b: t410_notri
use configuration work.t410_notri_struct_c0;
end for;
end for;
end t411_struct_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t411-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T411 system toplevel.
--
-- $Id: t411.vhd,v 1.1.1.1 2006/05/06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t411 is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(1 downto 0);
io_g_b : inout std_logic_vector(2 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end t411;
use work.t400_system_comp_pack.t410_notri;
architecture struct of t411 is
signal io_l_from_t410_s,
io_l_en_s : std_logic_vector(7 downto 0);
signal io_d_from_t410_s,
io_d_en_s : std_logic_vector(3 downto 0);
signal io_g_to_t410_s,
io_g_from_t410_s,
io_g_en_s : std_logic_vector(3 downto 0);
signal so_s,
so_en_s : std_logic;
signal sk_s,
sk_en_s : std_logic;
signal gnd_s : std_logic;
begin
gnd_s <= '0';
-----------------------------------------------------------------------------
-- T411 without tri-states
-----------------------------------------------------------------------------
t410_notri_b : t410_notri
generic map (
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => t400_opt_cko_crystal_c,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_d_out_type_3_g => t400_opt_out_type_std_c,
opt_d_out_type_2_g => t400_opt_out_type_std_c,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => t400_opt_out_type_std_c,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
reset_n_i => reset_n_i,
cko_i => gnd_s,
io_l_i => io_l_b,
io_l_o => io_l_from_t410_s,
io_l_en_o => io_l_en_s,
io_d_o => io_d_from_t410_s,
io_d_en_o => io_d_en_s,
io_g_i => io_g_to_t410_s,
io_g_o => io_g_from_t410_s,
io_g_en_o => io_g_en_s,
si_i => si_i,
so_o => so_s,
so_en_o => so_en_s,
sk_o => sk_s,
sk_en_o => sk_en_s
);
-----------------------------------------------------------------------------
-- Tri-states for output drivers
-----------------------------------------------------------------------------
io_l_tri: for idx in 7 downto 0 generate
io_l_b(idx) <= io_l_from_t410_s(idx)
when io_l_en_s(idx) = '1' else
'Z';
end generate;
--
io_d_tri: for idx in 1 downto 0 generate
io_d_o(idx) <= io_d_from_t410_s(idx)
when io_d_en_s(idx) = '1' else
'Z';
end generate;
--
io_g_tri: for idx in 2 downto 0 generate
io_g_b(idx) <= io_g_from_t410_s(idx)
when io_g_en_s(idx) = '1' else
'Z';
end generate;
io_g_to_t410_s <= io_g_from_t410_s(3) & io_g_b;
--
so_o <= so_s
when so_en_s = '1' else
'Z';
--
sk_o <= sk_s
when sk_en_s = '1' else
'Z';
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t411.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T420 system toplevel.
--
-- $Id: t420-c.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
configuration t420_struct_c0 of t420 is
for struct
for t420_notri_b: t420_notri
use configuration work.t420_notri_struct_c0;
end for;
end for;
end t420_struct_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t420-c.vhd,v $
-- Revision 1.1.1.1 2006/06/10 17:50:15 arnim
-- copied from opencores.org repository, pre-1.0 release on 10-Jun-2006
--
-- Revision 1.1 2006/05/14 22:29:01 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T420 system toplevel.
--
-- $Id: t420.vhd,v 1.1.1.2 2006/06/12 18:12:58 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t420 is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_8_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end t420;
use work.t400_system_comp_pack.t420_notri;
architecture struct of t420 is
signal io_l_from_t420_s,
io_l_en_s : std_logic_vector(7 downto 0);
signal io_d_from_t420_s,
io_d_en_s : std_logic_vector(3 downto 0);
signal io_g_from_t420_s,
io_g_en_s : std_logic_vector(3 downto 0);
signal so_s,
so_en_s : std_logic;
signal sk_s,
sk_en_s : std_logic;
begin
-----------------------------------------------------------------------------
-- T420 without tri-states
-----------------------------------------------------------------------------
t420_notri_b : t420_notri
generic map (
opt_type_g => t400_opt_type_420_c,
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => opt_cko_g,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => opt_microbus_g,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
reset_n_i => reset_n_i,
cko_i => cko_i,
io_l_i => io_l_b,
io_l_o => io_l_from_t420_s,
io_l_en_o => io_l_en_s,
io_d_o => io_d_from_t420_s,
io_d_en_o => io_d_en_s,
io_g_i => io_g_b,
io_g_o => io_g_from_t420_s,
io_g_en_o => io_g_en_s,
io_in_i => io_in_i,
si_i => si_i,
so_o => so_s,
so_en_o => so_en_s,
sk_o => sk_s,
sk_en_o => sk_en_s
);
-----------------------------------------------------------------------------
-- Tri-states for output drivers
-----------------------------------------------------------------------------
io_l_tri: for idx in 7 downto 0 generate
io_l_b(idx) <= io_l_from_t420_s(idx)
when io_l_en_s(idx) = '1' else
'Z';
end generate;
--
io_d_tri: for idx in 3 downto 0 generate
io_d_o(idx) <= io_d_from_t420_s(idx)
when io_d_en_s(idx) = '1' else
'Z';
end generate;
--
io_g_tri: for idx in 3 downto 0 generate
io_g_b(idx) <= io_g_from_t420_s(idx)
when io_g_en_s(idx) = '1' else
'Z';
end generate;
--
so_o <= so_s
when so_en_s = '1' else
'Z';
--
sk_o <= sk_s
when sk_en_s = '1' else
'Z';
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t420.vhd,v $
-- Revision 1.1.1.2 2006/06/12 18:12:58 arnim
-- copied from opencores.org repository, 1.0 release
--
-- Revision 1.6 2006/06/11 13:49:18 arniml
-- * hand generic opt_type_g down to t420_notri
-- * full generic list
--
-- Revision 1.5 2006/06/05 20:04:11 arniml
-- connect microbus generic
--
-- Revision 1.4 2006/05/23 01:16:05 arniml
-- routi CKO to t400_core
--
-- Revision 1.3 2006/05/20 02:49:04 arniml
-- select CK divide by 8
--
-- Revision 1.2 2006/05/17 00:38:31 arniml
-- connect missing input direction for IO G
--
-- Revision 1.1 2006/05/14 22:29:01 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T420/421 controller toplevel without tri-states.
--
-- $Id: t420_notri-c.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t420_notri_struct_c0 of t420_notri is
for struct
for core_b: t400_core
use configuration work.t400_core_struct_c0;
end for;
for pmem_b: t420_rom
use configuration work.t420_rom_struct_c0;
end for;
for dmem_b: generic_ram_ena
use configuration work.generic_ram_ena_rtl_c0;
end for;
for por_b: t400_por
use configuration work.t400_por_rtl_c0;
end for;
end for;
end t420_notri_struct_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t420_notri-c.vhd,v $
-- Revision 1.1.1.1 2006/06/10 17:50:15 arnim
-- copied from opencores.org repository, pre-1.0 release on 10-Jun-2006
--
-- Revision 1.2 2006/06/05 20:03:11 arniml
-- include generic_ram_ena
--
-- Revision 1.1 2006/05/14 22:29:01 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T420/421 controller toplevel without tri-states.
--
-- $Id: t420_notri.vhd,v 1.1.1.2 2006/06/12 18:12:58 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t420_notri is
generic (
opt_type_g : integer := t400_opt_type_420_c;
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end t420_notri;
use work.t400_core_comp_pack.t400_core;
use work.t400_tech_comp_pack.t400_por;
use work.t400_tech_comp_pack.generic_ram_ena;
architecture struct of t420_notri is
component t420_rom
port (
ck_i : in std_logic;
addr_i : in std_logic_vector(9 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end component;
signal por_n_s : std_logic;
signal pm_addr_s : std_logic_vector(9 downto 0);
signal pm_data_s : std_logic_vector(7 downto 0);
signal dm_addr_s : std_logic_vector(5 downto 0);
signal dm_we_s : std_logic;
signal dm_data_to_core_s,
dm_data_from_core_s : std_logic_vector(3 downto 0);
begin
-----------------------------------------------------------------------------
-- T400 core
-----------------------------------------------------------------------------
core_b : t400_core
generic map (
opt_type_g => opt_type_g,
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => opt_cko_g,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => opt_microbus_g,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
por_n_i => por_n_s,
reset_n_i => reset_n_i,
cko_i => cko_i,
pm_addr_o => pm_addr_s,
pm_data_i => pm_data_s,
dm_addr_o => dm_addr_s,
dm_we_o => dm_we_s,
dm_data_o => dm_data_from_core_s,
dm_data_i => dm_data_to_core_s,
io_l_i => io_l_i,
io_l_o => io_l_o,
io_l_en_o => io_l_en_o,
io_d_o => io_d_o,
io_d_en_o => io_d_en_o,
io_g_i => io_g_i,
io_g_o => io_g_o,
io_g_en_o => io_g_en_o,
io_in_i => io_in_i,
si_i => si_i,
so_o => so_o,
so_en_o => so_en_o,
sk_o => sk_o,
sk_en_o => sk_en_o
);
-----------------------------------------------------------------------------
-- Program memory
-----------------------------------------------------------------------------
pmem_b : t420_rom
port map (
ck_i => ck_i,
addr_i => pm_addr_s,
data_o => pm_data_s
);
-----------------------------------------------------------------------------
-- Data memory
-----------------------------------------------------------------------------
dmem_b : generic_ram_ena
generic map (
addr_width_g => 6,
data_width_g => 4
)
port map (
clk_i => ck_i,
a_i => dm_addr_s,
we_i => dm_we_s,
ena_i => ck_en_i,
d_i => dm_data_from_core_s,
d_o => dm_data_to_core_s
);
-----------------------------------------------------------------------------
-- Power-on reset circuit
-----------------------------------------------------------------------------
por_b : t400_por
generic map (
delay_g => 4,
cnt_width_g => 2
)
port map (
clk_i => ck_i,
por_n_o => por_n_s
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t420_notri.vhd,v $
-- Revision 1.1.1.2 2006/06/12 18:12:58 arnim
-- copied from opencores.org repository, 1.0 release
--
-- Revision 1.3 2006/06/11 13:48:43 arniml
-- hand generic opt_type_g down to t400_core
--
-- Revision 1.2 2006/06/05 20:03:52 arniml
-- connect microbus generic and include generic_ram_ena
--
-- Revision 1.1 2006/05/14 22:29:01 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T420/421 ROM.
--
-- $Id: t420_rom-e.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t420_rom is
port (
ck_i : in std_logic;
addr_i : in std_logic_vector(9 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end t420_rom;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t420_rom-e.vhd,v $
-- Revision 1.1.1.1 2006/06/10 17:50:15 arnim
-- copied from opencores.org repository, pre-1.0 release on 10-Jun-2006
--
-- Revision 1.1 2006/05/14 22:29:01 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T420/421 ROM.
--
-- $Id: t420_rom-struct-a.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
architecture struct of t420_rom is
component rom_t42x
port(
Clk : in std_logic;
A : in std_logic_vector(9 downto 0);
D : out std_logic_vector(7 downto 0)
);
end component;
begin
rom_b : rom_t42x
port map (
Clk => ck_i,
A => addr_i,
D => data_o
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t420_rom-struct-a.vhd,v $
-- Revision 1.1.1.1 2006/06/10 17:50:15 arnim
-- copied from opencores.org repository, pre-1.0 release on 10-Jun-2006
--
-- Revision 1.1 2006/06/05 22:44:29 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T421 system toplevel.
--
-- $Id: t421-c.vhd,v 1.1.1.1 2006/06/12 18:12:58 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
configuration t421_struct_c0 of t421 is
for struct
for t420_notri_b: t420_notri
use configuration work.t420_notri_struct_c0;
end for;
end for;
end t421_struct_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t421-c.vhd,v $
-- Revision 1.1.1.1 2006/06/12 18:12:58 arnim
-- copied from opencores.org repository, 1.0 release
--
-- Revision 1.1 2006/06/11 13:47:24 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T421 system toplevel.
--
-- $Id: t421.vhd,v 1.1.1.1 2006/06/12 18:12:58 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t421 is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_8_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end t421;
use work.t400_system_comp_pack.t420_notri;
architecture struct of t421 is
signal io_l_from_t420_s,
io_l_en_s : std_logic_vector(7 downto 0);
signal io_d_from_t420_s,
io_d_en_s : std_logic_vector(3 downto 0);
signal io_g_from_t420_s,
io_g_en_s : std_logic_vector(3 downto 0);
signal so_s,
so_en_s : std_logic;
signal sk_s,
sk_en_s : std_logic;
signal vdd4_s : std_logic_vector(3 downto 0);
begin
vdd4_s <= (others => '1');
-----------------------------------------------------------------------------
-- T420 without tri-states in T421 configuration
-----------------------------------------------------------------------------
t420_notri_b : t420_notri
generic map (
opt_type_g => t400_opt_type_421_c,
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => opt_cko_g,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => t400_opt_no_microbus_c,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
reset_n_i => reset_n_i,
cko_i => cko_i,
io_l_i => io_l_b,
io_l_o => io_l_from_t420_s,
io_l_en_o => io_l_en_s,
io_d_o => io_d_from_t420_s,
io_d_en_o => io_d_en_s,
io_g_i => io_g_b,
io_g_o => io_g_from_t420_s,
io_g_en_o => io_g_en_s,
io_in_i => vdd4_s,
si_i => si_i,
so_o => so_s,
so_en_o => so_en_s,
sk_o => sk_s,
sk_en_o => sk_en_s
);
-----------------------------------------------------------------------------
-- Tri-states for output drivers
-----------------------------------------------------------------------------
io_l_tri: for idx in 7 downto 0 generate
io_l_b(idx) <= io_l_from_t420_s(idx)
when io_l_en_s(idx) = '1' else
'Z';
end generate;
--
io_d_tri: for idx in 3 downto 0 generate
io_d_o(idx) <= io_d_from_t420_s(idx)
when io_d_en_s(idx) = '1' else
'Z';
end generate;
--
io_g_tri: for idx in 3 downto 0 generate
io_g_b(idx) <= io_g_from_t420_s(idx)
when io_g_en_s(idx) = '1' else
'Z';
end generate;
--
so_o <= so_s
when so_en_s = '1' else
'Z';
--
sk_o <= sk_s
when sk_en_s = '1' else
'Z';
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t421.vhd,v $
-- Revision 1.1.1.1 2006/06/12 18:12:58 arnim
-- copied from opencores.org repository, 1.0 release
--
-- Revision 1.1 2006/06/11 13:47:24 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Arithmetic Logic Unit (ALU).
-- It contains the accumulator and the C flag.
--
-- $Id: t400_alu-c.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_alu_rtl_c0 of t400_alu is
for rtl
end for;
end t400_alu_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_alu-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Arithmetic Logic Unit (ALU).
-- It contains the accumulator and the C flag.
--
-- $Id: t400_alu.vhd,v 1.3 2006/05/22 00:01:56 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.all;
use work.t400_opt_pack.all;
entity t400_alu is
generic (
opt_cko_g : integer := t400_opt_cko_crystal_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
cko_i : in std_logic;
-- Control Interface ------------------------------------------------------
op_i : in alu_op_t;
-- Data Interface ---------------------------------------------------------
m_i : in dw_t;
dec_data_i : in dec_data_t;
q_low_i : in dw_t;
b_i : in b_t;
g_i : in dw_t;
in_i : in dw_t;
sio_i : in dw_t;
a_o : out dw_t;
carry_o : out std_logic;
c_o : out std_logic
);
end t400_alu;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_alu is
subtype alu_dw_t is unsigned(dw_t'high+1 downto 0);
signal alu_result_s : alu_dw_t;
signal a_q : dw_t;
signal c_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process regs
--
-- Purpose:
-- Implements the sequential registers of the ALU:
-- * A - accumulator
-- * C - carry flag
--
regs: process (ck_i, por_i)
begin
if por_i then
a_q <= (others => '0');
c_q <= '0';
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
a_q <= (others => '0');
c_q <= '0';
elsif ck_en_i then
-- update accumulator
case op_i is
when ALU_CLRA |
ALU_ADD |
ALU_ADD_10 |
ALU_ADD_C |
ALU_ADD_DEC |
ALU_COMP |
ALU_XOR =>
a_q <= std_logic_vector(alu_result_s(dw_t'range));
when ALU_LOAD_M =>
a_q <= m_i;
when ALU_LOAD_Q =>
a_q <= q_low_i;
when ALU_LOAD_G =>
a_q <= g_i;
when ALU_LOAD_IN =>
a_q <= in_i;
when ALU_LOAD_IL =>
a_q(3) <= in_i(3);
if opt_cko_g = t400_opt_cko_gpi_c then
a_q(2) <= cko_i;
else
a_q(2) <= '1';
end if;
a_q(1) <= '0';
a_q(0) <= in_i(0);
when ALU_LOAD_BR =>
a_q(3 downto 2) <= (others => '0');
a_q(1 downto 0) <= b_i(br_range_t);
when ALU_LOAD_BD =>
a_q <= b_i(bd_range_t);
when ALU_LOAD_SIO =>
a_q <= sio_i;
when others =>
null;
end case;
-- update C flag upon the following instructions
case op_i is
-- carry result of addition -----------------------------------------
when ALU_ADD_C =>
c_q <= alu_result_s(alu_dw_t'high);
-- reset C flag -----------------------------------------------------
when ALU_RC =>
c_q <= '0';
-- set C flag -------------------------------------------------------
when ALU_SC =>
c_q <= '1';
when others =>
null;
end case;
end if;
end if;
end process regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process dp
--
-- Purpose:
-- Implements the ALU's data path.
--
dp: process (op_i,
a_q,
m_i,
dec_data_i,
c_q)
variable in1_v,
in2_v,
in3_v,
add_v, xor_v : alu_dw_t;
begin
-- prepare adder
in1_v := '0' & unsigned(a_q);
if op_i = ALU_ADD_10 then
in2_v := to_unsigned(10, alu_dw_t'length);
elsif op_i = ALU_ADD_DEC then
in2_v := '0' & unsigned(dec_data_i(dw_t'range));
else
in2_v := '0' & unsigned(m_i);
end if;
if op_i = ALU_ADD_C then
in3_v := (others => '0');
in3_v(0) := c_q;
else
in3_v := (others => '0');
end if;
add_v := in1_v + in2_v + in3_v;
-- prepare exclusive or
xor_v := in1_v xor in2_v;
case op_i is
-- ALU operation: Clear accumulator -------------------------------------
when ALU_CLRA =>
alu_result_s <= (others => '0');
-- ALU operation: Add to accumulator ------------------------------------
when ALU_ADD |
ALU_ADD_10 |
ALU_ADD_C |
ALU_ADD_DEC =>
alu_result_s <= add_v;
-- ALU operation: Complement accumulator --------------------------------
when ALU_COMP =>
alu_result_s <= '0' & not unsigned(a_q);
-- ALU operation: XOR to accumulator ------------------------------------
when ALU_XOR =>
alu_result_s <= xor_v;
when others =>
alu_result_s <= (others => '-');
end case;
end process dp;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
a_o <= a_q;
carry_o <= alu_result_s(alu_dw_t'high);
c_o <= c_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_alu.vhd,v $
-- Revision 1.3 2006/05/22 00:01:56 arniml
-- simplify ININ/INIL instruction support
--
-- Revision 1.2 2006/05/21 21:47:40 arniml
-- route cko to ALU for INIL instruction
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The clock generation unit.
-- PHI1 clock and input/output clock enables are generated here.
--
-- $Id: t400_clkgen-c.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_clkgen_rtl_c0 of t400_clkgen is
for rtl
end for;
end t400_clkgen_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_clkgen-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The clock generation unit.
-- PHI1 clock and input/output clock enables are generated here.
--
-- $Id: t400_clkgen.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t400_clkgen is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
-- Clock Interface --------------------------------------------------------
phi1_o : out std_logic;
out_en_o : out boolean;
in_en_o : out boolean;
icyc_en_o : out boolean
);
end t400_clkgen;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_clkgen is
subtype ck_div_t is unsigned(5 downto 0);
type ck_div_a_t is array(natural range t400_opt_ck_div_32_c
downto t400_opt_ck_div_4_c) of
ck_div_t;
-- reload values for the CK dividing counter
constant ck_div_a_c : ck_div_a_t := (
t400_opt_ck_div_32_c => to_unsigned(31, ck_div_t'length),
t400_opt_ck_div_16_c => to_unsigned(15, ck_div_t'length),
t400_opt_ck_div_8_c => to_unsigned( 7, ck_div_t'length),
t400_opt_ck_div_4_c => to_unsigned( 3, ck_div_t'length));
signal ck_div_cnt_q : ck_div_t;
signal ck_div_zero_s,
ck_div_half_s : boolean;
signal phi1_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process ck_div
--
-- Purpose:
-- Divide the incoming clock on ck_i and generate the derived clock
-- enable for the core.
--
ck_div: process (ck_i, por_i)
begin
if por_i then
ck_div_cnt_q <= ck_div_a_c(opt_ck_div_g);
phi1_q <= '0';
elsif ck_i'event and ck_i = '1' then
if ck_en_i then
if ck_div_zero_s then
ck_div_cnt_q <= ck_div_a_c(opt_ck_div_g);
phi1_q <= '0';
else
ck_div_cnt_q <= ck_div_cnt_q - 1;
if ck_div_half_s then
phi1_q <= '1';
end if;
end if;
end if;
end if;
end process ck_div;
--
ck_div_zero_s <= ck_div_cnt_q = 0;
ck_div_half_s <= ck_div_cnt_q = SHIFT_RIGHT(ck_div_a_c(opt_ck_div_g), 1) + 1;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
phi1_o <= phi1_q;
-- Instruction cycle enable
icyc_en_o <= ck_en_i and ck_div_zero_s;
-- Output update enable
out_en_o <= ck_en_i and ck_div_zero_s;
-- Input sample enable
in_en_o <= ck_en_i and ck_div_half_s;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_clkgen.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- $Id: t400_comp_pack-p.vhd,v 1.7 2006/06/05 20:31:56 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
package t400_comp_pack is
component t400_clkgen
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
-- Clock Interface ------------------------------------------------------
phi1_o : out std_logic;
out_en_o : out boolean;
in_en_o : out boolean;
icyc_en_o : out boolean
);
end component;
component t400_reset
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
icyc_en_i : in boolean;
-- Reset Interface ------------------------------------------------------
por_i : in boolean;
reset_n_i : in std_logic;
res_o : out boolean
);
end component;
component t400_stack
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
-- Stack Control Interface ----------------------------------------------
op_i : in stack_op_t;
-- Program Counter Interface --------------------------------------------
pc_i : in pc_t;
pc_o : out pc_t
);
end component;
component t400_pmem_ctrl
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
a_i : in dw_t;
m_i : in dw_t;
-- Control Interface ----------------------------------------------------
op_i : in pc_op_t;
dec_data_i : in dec_data_t;
-- Stack Interface ------------------------------------------------------
pc_o : out pc_t;
pc_i : in pc_t;
-- Program Memory Interface ---------------------------------------------
pm_addr_o : out pc_t
);
end component;
component t400_alu
generic (
opt_cko_g : integer := t400_opt_cko_crystal_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
cko_i : in std_logic;
-- Control Interface ----------------------------------------------------
op_i : in alu_op_t;
-- Data Interface -------------------------------------------------------
m_i : in dw_t;
dec_data_i : in dec_data_t;
q_low_i : in dw_t;
b_i : in b_t;
g_i : in dw_t;
in_i : in dw_t;
sio_i : in dw_t;
a_o : out dw_t;
carry_o : out std_logic;
c_o : out std_logic
);
end component;
component t400_dmem_ctrl
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ----------------------------------------------------
dmem_op_i : in dmem_op_t;
b_op_i : in b_op_t;
dec_data_i : in dec_data_t;
a_i : in dw_t;
q_high_i : in dw_t;
b_o : out b_t;
-- Data Memory Interface ------------------------------------------------
dm_addr_o : out dm_addr_t;
dm_data_i : in dw_t;
dm_data_o : out dw_t;
dm_we_o : out std_logic
);
end component;
component t400_opc_table
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
opcode_i : in byte_t;
mnemonic_o : out mnemonic_t;
multi_byte_o : out boolean
);
end component;
component t400_decoder
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
out_en_i : in boolean;
in_en_i : in boolean;
icyc_en_i : in boolean;
-- Module Control Interface ---------------------------------------------
pc_op_o : out pc_op_t;
stack_op_o : out stack_op_t;
dmem_op_o : out dmem_op_t;
b_op_o : out b_op_t;
skip_op_o : out skip_op_t;
alu_op_o : out alu_op_t;
io_l_op_o : out io_l_op_t;
io_d_op_o : out io_d_op_t;
io_g_op_o : out io_g_op_t;
io_in_op_o : out io_in_op_t;
sio_op_o : out sio_op_t;
dec_data_o : out dec_data_t;
en_o : out dw_t;
-- Skip Interface -------------------------------------------------------
skip_i : in boolean;
skip_lbi_i : in boolean;
is_lbi_o : out boolean;
int_i : in boolean;
-- Program Memory Interface ---------------------------------------------
pm_addr_i : in pc_t;
pm_data_i : in byte_t
);
end component;
component t400_skip
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ----------------------------------------------------
op_i : in skip_op_t;
dec_data_i : in dec_data_t;
carry_i : in std_logic;
c_i : in std_logic;
bd_i : in dw_t;
is_lbi_i : in boolean;
skip_o : out boolean;
skip_lbi_o : out boolean;
-- Data Interface -------------------------------------------------------
a_i : in dw_t;
m_i : in dw_t;
g_i : in dw_t;
tim_c_i : in boolean
);
end component;
component t400_io_l
generic (
opt_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
in_en_i : in boolean;
-- Control Interface ----------------------------------------------------
op_i : in io_l_op_t;
en2_i : in std_logic;
m_i : in dw_t;
a_i : in dw_t;
pm_data_i : in byte_t;
q_o : out byte_t;
-- Microbus Interface ---------------------------------------------------
cs_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
-- Port L Interface -----------------------------------------------------
io_l_i : in byte_t;
io_l_o : out byte_t;
io_l_en_o : out byte_t
);
end component;
component t400_io_d
generic (
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ----------------------------------------------------
op_i : in io_d_op_t;
bd_i : in bd_t;
-- Port D Interface -----------------------------------------------------
io_d_o : out dw_t;
io_d_en_o : out dw_t
);
end component;
component t400_io_g
generic (
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
cs_n_i : in std_logic;
wr_n_i : in std_logic;
-- Control Interface ----------------------------------------------------
op_i : in io_g_op_t;
m_i : in dw_t;
dec_data_i : in dec_data_t;
-- Port G Interface -----------------------------------------------------
io_g_o : out dw_t;
io_g_en_o : out dw_t
);
end component;
component t400_io_in
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
icyc_en_i : in boolean;
in_en_i : in boolean;
-- Control Interface ----------------------------------------------------
op_i : in io_in_op_t;
en1_i : in std_logic;
-- Port Interface -------------------------------------------------------
io_in_i : in dw_t;
in_o : out dw_t;
int_o : out boolean
);
end component;
component t400_sio
generic (
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
phi1_i : in std_logic;
out_en_i : in boolean;
in_en_i : in boolean;
-- Control Interface ----------------------------------------------------
op_i : in sio_op_t;
en0_i : in std_logic;
en3_i : in std_logic;
-- SIO Interface --------------------------------------------------------
a_i : in dw_t;
c_i : in std_logic;
sio_o : out dw_t;
-- Pad Interface --------------------------------------------------------
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end component;
component t400_timer
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
icyc_en_i : in boolean;
-- Skip Interface -------------------------------------------------------
op_i : in skip_op_t;
c_o : out boolean
);
end component;
end t400_comp_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_comp_pack-p.vhd,v $
-- Revision 1.7 2006/06/05 20:31:56 arniml
-- microbus support for IO G added
--
-- Revision 1.6 2006/06/05 14:20:34 arniml
-- interface comments added
--
-- Revision 1.5 2006/05/27 19:11:33 arniml
-- updates for interrupt support
--
-- Revision 1.4 2006/05/22 00:03:08 arniml
-- io_in added
--
-- Revision 1.3 2006/05/21 21:47:40 arniml
-- route cko to ALU for INIL instruction
--
-- Revision 1.2 2006/05/20 02:48:17 arniml
-- timer module included
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T400 Microcontroller Core
--
-- $Id: t400_core-c.vhd,v 1.3 2006/05/22 00:03:29 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_core_struct_c0 of t400_core is
for struct
for clkgen_b: t400_clkgen
use configuration work.t400_clkgen_rtl_c0;
end for;
for reset_b: t400_reset
use configuration work.t400_reset_rtl_c0;
end for;
for pmem_ctrl_b: t400_pmem_ctrl
use configuration work.t400_pmem_ctrl_rtl_c0;
end for;
for dmem_ctrl_b: t400_dmem_ctrl
use configuration work.t400_dmem_ctrl_rtl_c0;
end for;
for decoder_b: t400_decoder
use configuration work.t400_decoder_rtl_c0;
end for;
for skip_b: t400_skip
use configuration work.t400_skip_rtl_c0;
end for;
for alu_b: t400_alu
use configuration work.t400_alu_rtl_c0;
end for;
for stack_b: t400_stack
use configuration work.t400_stack_rtl_c0;
end for;
for io_l_b: t400_io_l
use configuration work.t400_io_l_rtl_c0;
end for;
for io_d_b: t400_io_d
use configuration work.t400_io_d_rtl_c0;
end for;
for io_g_b: t400_io_g
use configuration work.t400_io_g_rtl_c0;
end for;
for use_in
for io_in_b: t400_io_in
use configuration work.t400_io_in_rtl_c0;
end for;
end for;
for sio_b: t400_sio
use configuration work.t400_sio_rtl_c0;
end for;
for use_tim
for timer_b: t400_timer
use configuration work.t400_timer_rtl_c0;
end for;
end for;
end for;
end t400_core_struct_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_core-c.vhd,v $
-- Revision 1.3 2006/05/22 00:03:29 arniml
-- io_in added
--
-- Revision 1.2 2006/05/20 02:48:17 arniml
-- timer module included
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- T400 Microcontroller Core
--
-- $Id: t400_core.vhd,v 1.10 2006/06/11 13:34:39 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t400_core is
generic (
opt_type_g : integer := t400_opt_type_420_c;
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
por_n_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
pm_addr_o : out std_logic_vector(9 downto 0);
pm_data_i : in std_logic_vector(7 downto 0);
dm_addr_o : out std_logic_vector(5 downto 0);
dm_we_o : out std_logic;
dm_data_o : out std_logic_vector(3 downto 0);
dm_data_i : in std_logic_vector(3 downto 0);
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end t400_core;
use work.t400_pack.all;
use work.t400_comp_pack.all;
architecture struct of t400_core is
signal ck_en_s : boolean;
signal por_s : boolean;
signal res_s : boolean;
signal phi1_s : std_logic;
signal out_en_s : boolean;
signal in_en_s : boolean;
signal icyc_en_s : boolean;
signal pm_addr_s : pc_t;
signal a_s : dw_t;
signal dec_data_s : dec_data_t;
signal pc_to_stack_s,
pc_from_stack_s : pc_t;
signal q_s : byte_t;
signal b_s : b_t;
signal c_s,
carry_s : std_logic;
signal sio_s : dw_t;
signal pc_op_s : pc_op_t;
signal stack_op_s : stack_op_t;
signal dmem_op_s : dmem_op_t;
signal b_op_s : b_op_t;
signal skip_op_s : skip_op_t;
signal alu_op_s : alu_op_t;
signal io_l_op_s : io_l_op_t;
signal io_d_op_s : io_d_op_t;
signal io_g_op_s : io_g_op_t;
signal io_in_op_s : io_in_op_t;
signal sio_op_s : sio_op_t;
signal is_lbi_s : boolean;
signal en_s : dw_t;
signal skip_s,
skip_lbi_s : boolean;
signal tim_c_s : boolean;
signal in_s : dw_t;
signal int_s : boolean;
signal io_g_s : std_logic_vector(io_g_i'range);
signal cs_n_s,
rd_n_s,
wr_n_s : std_logic;
signal vdd_s : std_logic;
signal gnd4_s : dw_t;
begin
-- dummies
vdd_s <= '1';
gnd4_s <= (others => '0');
ck_en_s <= ck_en_i = '1';
por_s <= por_n_i = '0';
io_g_s <= to_X01(io_g_i);
-----------------------------------------------------------------------------
-- Clock generator
-----------------------------------------------------------------------------
clkgen_b : t400_clkgen
generic map (
opt_ck_div_g => opt_ck_div_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
phi1_o => phi1_s,
out_en_o => out_en_s,
in_en_o => in_en_s,
icyc_en_o => icyc_en_s
);
-----------------------------------------------------------------------------
-- Reset module
-----------------------------------------------------------------------------
reset_b : t400_reset
port map (
ck_i => ck_i,
icyc_en_i => icyc_en_s,
por_i => por_s,
reset_n_i => reset_n_i,
res_o => res_s
);
-----------------------------------------------------------------------------
-- Program memory controller
-----------------------------------------------------------------------------
pmem_ctrl_b : t400_pmem_ctrl
generic map (
opt_type_g => opt_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
a_i => a_s,
m_i => dm_data_i,
op_i => pc_op_s,
dec_data_i => dec_data_s,
pc_o => pc_to_stack_s,
pc_i => pc_from_stack_s,
pm_addr_o => pm_addr_s
);
--
pm_addr_o <= std_logic_vector(pm_addr_s);
-----------------------------------------------------------------------------
-- Data memory controller
-----------------------------------------------------------------------------
dmem_ctrl_b : t400_dmem_ctrl
generic map (
opt_type_g => opt_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
dmem_op_i => dmem_op_s,
b_op_i => b_op_s,
dec_data_i => dec_data_s,
a_i => a_s,
q_high_i => q_s(7 downto 4),
b_o => b_s,
dm_addr_o => dm_addr_o,
dm_data_i => dm_data_i,
dm_data_o => dm_data_o,
dm_we_o => dm_we_o
);
-----------------------------------------------------------------------------
-- Decoder
-----------------------------------------------------------------------------
decoder_b : t400_decoder
generic map (
opt_type_g => opt_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
out_en_i => out_en_s,
in_en_i => in_en_s,
icyc_en_i => icyc_en_s,
pc_op_o => pc_op_s,
stack_op_o => stack_op_s,
dmem_op_o => dmem_op_s,
b_op_o => b_op_s,
skip_op_o => skip_op_s,
alu_op_o => alu_op_s,
io_l_op_o => io_l_op_s,
io_d_op_o => io_d_op_s,
io_g_op_o => io_g_op_s,
io_in_op_o => io_in_op_s,
sio_op_o => sio_op_s,
dec_data_o => dec_data_s,
en_o => en_s,
skip_i => skip_s,
skip_lbi_i => skip_lbi_s,
is_lbi_o => is_lbi_s,
int_i => int_s,
pm_addr_i => pm_addr_s,
pm_data_i => pm_data_i
);
-----------------------------------------------------------------------------
-- Skip logic
-----------------------------------------------------------------------------
skip_b : t400_skip
generic map (
opt_type_g => opt_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
op_i => skip_op_s,
dec_data_i => dec_data_s,
carry_i => carry_s,
c_i => c_s,
bd_i => b_s(bd_range_t),
is_lbi_i => is_lbi_s,
skip_o => skip_s,
skip_lbi_o => skip_lbi_s,
a_i => a_s,
m_i => dm_data_i,
g_i => io_g_s,
tim_c_i => tim_c_s
);
-----------------------------------------------------------------------------
-- ALU
-----------------------------------------------------------------------------
alu_b : t400_alu
generic map (
opt_cko_g => opt_cko_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
cko_i => cko_i,
op_i => alu_op_s,
m_i => dm_data_i,
dec_data_i => dec_data_s,
q_low_i => q_s(3 downto 0),
b_i => b_s,
g_i => io_g_s,
in_i => in_s,
sio_i => sio_s,
a_o => a_s,
carry_o => carry_s,
c_o => c_s
);
-----------------------------------------------------------------------------
-- Stack module
-----------------------------------------------------------------------------
stack_b : t400_stack
generic map (
opt_type_g => opt_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
op_i => stack_op_s,
pc_i => pc_to_stack_s,
pc_o => pc_from_stack_s
);
-----------------------------------------------------------------------------
-- IO L module
-----------------------------------------------------------------------------
cs_n_s <= io_in_i(2);
rd_n_s <= io_in_i(1);
wr_n_s <= io_in_i(3);
--
io_l_b : t400_io_l
generic map (
opt_out_type_7_g => opt_l_out_type_7_g,
opt_out_type_6_g => opt_l_out_type_6_g,
opt_out_type_5_g => opt_l_out_type_5_g,
opt_out_type_4_g => opt_l_out_type_4_g,
opt_out_type_3_g => opt_l_out_type_3_g,
opt_out_type_2_g => opt_l_out_type_2_g,
opt_out_type_1_g => opt_l_out_type_1_g,
opt_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => opt_microbus_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
in_en_i => in_en_s,
op_i => io_l_op_s,
en2_i => en_s(2),
m_i => dm_data_i,
a_i => a_s,
pm_data_i => pm_data_i,
q_o => q_s,
cs_n_i => cs_n_s,
rd_n_i => rd_n_s,
wr_n_i => wr_n_s,
io_l_i => io_l_i,
io_l_o => io_l_o,
io_l_en_o => io_l_en_o
);
-----------------------------------------------------------------------------
-- IO D module
-----------------------------------------------------------------------------
io_d_b : t400_io_d
generic map (
opt_out_type_3_g => opt_d_out_type_3_g,
opt_out_type_2_g => opt_d_out_type_2_g,
opt_out_type_1_g => opt_d_out_type_1_g,
opt_out_type_0_g => opt_d_out_type_0_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
op_i => io_d_op_s,
bd_i => b_s(bd_range_t),
io_d_o => io_d_o,
io_d_en_o => io_d_en_o
);
-----------------------------------------------------------------------------
-- IO G module
-----------------------------------------------------------------------------
io_g_b : t400_io_g
generic map (
opt_out_type_3_g => opt_g_out_type_3_g,
opt_out_type_2_g => opt_g_out_type_2_g,
opt_out_type_1_g => opt_g_out_type_1_g,
opt_out_type_0_g => opt_g_out_type_0_g,
opt_microbus_g => opt_microbus_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
cs_n_i => cs_n_s,
wr_n_i => wr_n_s,
op_i => io_g_op_s,
m_i => dm_data_i,
dec_data_i => dec_data_s,
io_g_o => io_g_o,
io_g_en_o => io_g_en_o
);
-----------------------------------------------------------------------------
-- IO IN module
-----------------------------------------------------------------------------
use_in: if opt_type_g = t400_opt_type_420_c generate
io_in_b : t400_io_in
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
icyc_en_i => icyc_en_s,
in_en_i => in_en_s,
op_i => io_in_op_s,
en1_i => en_s(1),
io_in_i => io_in_i,
in_o => in_s,
int_o => int_s
);
end generate;
no_in: if opt_type_g /= t400_opt_type_420_c generate
in_s <= (others => '0');
int_s <= false;
end generate;
-----------------------------------------------------------------------------
-- SIO module
-----------------------------------------------------------------------------
sio_b : t400_sio
generic map (
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
res_i => res_s,
phi1_i => phi1_s,
out_en_i => out_en_s,
in_en_i => in_en_s,
op_i => sio_op_s,
en0_i => en_s(0),
en3_i => en_s(3),
a_i => a_s,
c_i => c_s,
sio_o => sio_s,
si_i => si_i,
so_o => so_o,
so_en_o => so_en_o,
sk_o => sk_o,
sk_en_o => sk_en_o
);
-----------------------------------------------------------------------------
-- Timer module
-----------------------------------------------------------------------------
use_tim: if opt_type_g = t400_opt_type_420_c or
opt_type_g = t400_opt_type_421_c generate
timer_b : t400_timer
port map (
ck_i => ck_i,
ck_en_i => ck_en_s,
por_i => por_s,
icyc_en_i => icyc_en_s,
op_i => skip_op_s,
c_o => tim_c_s
);
end generate;
notim: if opt_type_g /= t400_opt_type_420_c and
opt_type_g /= t400_opt_type_421_c generate
tim_c_s <= false;
end generate;
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_core.vhd,v $
-- Revision 1.10 2006/06/11 13:34:39 arniml
-- Fix bug:
-- "Timer skipped in T421 configuration"
-- The generate block that instantiates the timer module considers
-- now t400_opt_type_421_x as well.
--
-- Revision 1.9 2006/06/06 00:33:56 arniml
-- remove note about limitations
--
-- Revision 1.8 2006/06/05 20:34:21 arniml
-- use dedicated microbus cs/rd/wr strobes
--
-- Revision 1.7 2006/06/05 14:19:15 arniml
-- connect microbus control signals to IO L
--
-- Revision 1.6 2006/05/27 19:11:33 arniml
-- updates for interrupt support
--
-- Revision 1.5 2006/05/23 01:13:56 arniml
-- use to_X01 for G input
--
-- Revision 1.4 2006/05/22 00:03:29 arniml
-- io_in added
--
-- Revision 1.3 2006/05/21 21:47:40 arniml
-- route cko to ALU for INIL instruction
--
-- Revision 1.2 2006/05/20 02:48:17 arniml
-- timer module included
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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@@ -0,0 +1,82 @@
-------------------------------------------------------------------------------
--
-- $Id: t400_core_comp_pack-p.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
package t400_core_comp_pack is
component t400_core
generic (
opt_type_g : integer := t400_opt_type_420_c;
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
por_n_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
pm_addr_o : out std_logic_vector(9 downto 0);
pm_data_i : in std_logic_vector(7 downto 0);
dm_addr_o : out std_logic_vector(5 downto 0);
dm_we_o : out std_logic;
dm_data_o : out std_logic_vector(3 downto 0);
dm_data_i : in std_logic_vector(3 downto 0);
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end component;
end t400_core_comp_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_core_comp_pack-p.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The decoder unit.
-- Implements the instruction opcodes and controls all units of the T400 core.
--
-- $Id: t400_decoder-c.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_decoder_rtl_c0 of t400_decoder is
for rtl
for opc_table_b: t400_opc_table
use configuration work.t400_opc_table_rtl_c0;
end for;
end for;
end t400_decoder_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_decoder-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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@@ -0,0 +1,884 @@
-------------------------------------------------------------------------------
--
-- The decoder unit.
-- Implements the instruction opcodes and controls all units of the T400 core.
--
-- $Id: t400_decoder.vhd,v 1.6 2006/06/05 14:20:34 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_decoder is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
out_en_i : in boolean;
in_en_i : in boolean;
icyc_en_i : in boolean;
-- Module Control Interface -----------------------------------------------
pc_op_o : out pc_op_t;
stack_op_o : out stack_op_t;
dmem_op_o : out dmem_op_t;
b_op_o : out b_op_t;
skip_op_o : out skip_op_t;
alu_op_o : out alu_op_t;
io_l_op_o : out io_l_op_t;
io_d_op_o : out io_d_op_t;
io_g_op_o : out io_g_op_t;
io_in_op_o : out io_in_op_t;
sio_op_o : out sio_op_t;
dec_data_o : out dec_data_t;
en_o : out dw_t;
-- Skip Interface ---------------------------------------------------------
skip_i : in boolean;
skip_lbi_i : in boolean;
is_lbi_o : out boolean;
int_i : in boolean;
-- Program Memory Interface -----------------------------------------------
pm_addr_i : in pc_t;
pm_data_i : in byte_t
);
end t400_decoder;
library ieee;
use ieee.numeric_std.all;
use work.t400_comp_pack.t400_opc_table;
architecture rtl of t400_decoder is
signal cyc_cnt_q : unsigned(2 downto 0);
signal ibyte1_q,
ibyte2_q : byte_t;
signal opcode_s : byte_t;
signal second_cyc_q : boolean;
signal mnemonic_s,
mnemonic_q : mnemonic_t;
signal multi_byte_s,
multi_byte_q : boolean;
signal last_cycle_s : boolean;
signal force_mc_s : boolean;
signal en_q : dw_t;
signal set_en_s : boolean;
signal ack_int_s : boolean;
begin
-----------------------------------------------------------------------------
-- Theory of operation:
--
-- a) One instruction cycle lasts at least 4 ck_i cycles.
-- b) PC for instruction/parameter fetch must be valid during cycle 2.
-- => cycle 2 is the opcode fetch cycle
-- c) Cycle 3 is the opcode decode cycle.
-- => opcode_s is valid with cycle 3
-- d) mnemonic_q is then valid with cycle 0 until end of instruction.
-- So is ibyte1_q.
-- e) PC for is incremented during last instruction cycle.
-- => fetch of either new instruction or second instruction byte
-- f) Second instruction byte is saved in ibyte2_q for cycle 0.
-- Valid until end of instruction.
--
-- Constraints:
--
-- a) PC of next instruction must be pushed in cycle 0 or 1.
-- b) PC for next instruction must be poped latest in cycle 1.
-- c) PC for next instruction can only be calculated latest in cycle 1.
-- d) IO output is enabled by out_en_i
-- e) IO inputs are sampled with in_en_i
--
-- d) and e) are required for proper timing in relation to phi1
-- (SK clock/sync output).
--
-- Conventions:
--
-- a) ALU operations take place in cycle 1.
--
-----------------------------------------------------------------------------
last_cycle_s <= (not multi_byte_q and
not second_cyc_q and not force_mc_s)
or
second_cyc_q;
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the various sequential elements.
-- Cycle counter:
-- It identifies the execution cycle of the
-- current instruction.
-- Instruction registers:
-- They save the first and second byte of an instruction for
-- further processing.
-- New instruction flag:
-- Indicates when a new instruction is fetched from the program
-- memory. Implemented as a flip-flop to control the multiplexer
-- which saves power by gating the combinational opcode decoder.
-- Mnemonic register:
-- Latches the decoded mnemonic of the current instruction.
-- Multi byte flag:
-- Latches the decoded multi byte status information.
--
seq: process (ck_i, por_i)
begin
if por_i then
cyc_cnt_q <= to_unsigned(1, cyc_cnt_q'length);
second_cyc_q <= false;
ibyte1_q <= (others => '0');
ibyte2_q <= (others => '0');
mnemonic_q <= MN_CLRA;
multi_byte_q <= false;
en_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
mnemonic_q <= MN_CLRA;
multi_byte_q <= false;
cyc_cnt_q <= (others => '0');
en_q <= (others => '0');
elsif ck_en_i then
-- cycle counter ------------------------------------------------------
if icyc_en_i then
-- new instruction cycle started
cyc_cnt_q <= (others => '0');
elsif cyc_cnt_q /= 4 then
cyc_cnt_q <= cyc_cnt_q + 1;
end if;
-- second cycle flag --------------------------------------------------
if icyc_en_i then
if not last_cycle_s then
second_cyc_q <= true;
else
second_cyc_q <= false;
end if;
end if;
-- instruction byte 1 and mnemonic info -------------------------------
if icyc_en_i and last_cycle_s then
if not ack_int_s then
-- update instruction descriptors in normal mode
ibyte1_q <= pm_data_i;
mnemonic_q <= mnemonic_s;
multi_byte_q <= multi_byte_s;
else
-- force NOP instruction when vectoring to interrupt routine
ibyte1_q <= "01000100";
mnemonic_q <= MN_NOP;
multi_byte_q <= false;
end if;
end if;
-- instruction byte 2 -------------------------------------------------
if icyc_en_i and not last_cycle_s then
ibyte2_q <= pm_data_i;
end if;
-- EN register --------------------------------------------------------
if set_en_s then
en_q <= ibyte2_q(dw_range_t);
elsif ack_int_s then
-- reset interrupt enable when INT has been acknowledged
en_q(1) <= '0';
end if;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Opcode multiplexer
-----------------------------------------------------------------------------
opcode_s <= pm_data_i
when icyc_en_i else
ibyte1_q;
-----------------------------------------------------------------------------
-- Opcode decoder table
-----------------------------------------------------------------------------
opc_table_b : t400_opc_table
generic map (
opt_type_g => opt_type_g
)
port map (
opcode_i => opcode_s,
mnemonic_o => mnemonic_s,
multi_byte_o => multi_byte_s
);
-----------------------------------------------------------------------------
-- Process decoder_ctrl
--
-- Purpose:
-- Implements the controlling logic of the decoder module.
--
decoder_ctrl: process (icyc_en_i,
out_en_i, in_en_i,
cyc_cnt_q,
mnemonic_q, second_cyc_q, last_cycle_s,
ibyte1_q, ibyte2_q,
skip_i, skip_lbi_i,
en_q, int_i,
pm_addr_i, pm_data_i)
variable cyc_v : natural range 0 to 4;
variable t41x_type_v,
t420_type_v : boolean;
variable en_int_v : boolean;
begin
-- default assignments
pc_op_o <= PC_NONE;
stack_op_o <= STACK_NONE;
dmem_op_o <= DMEM_RB; -- default is read via B
b_op_o <= B_NONE;
skip_op_o <= SKIP_NONE;
alu_op_o <= ALU_NONE;
io_l_op_o <= IOL_NONE;
io_d_op_o <= IOD_NONE;
io_g_op_o <= IOG_NONE;
io_in_op_o <= IOIN_NONE;
sio_op_o <= SIO_NONE;
dec_data_o <= (others => '0');
is_lbi_o <= false;
set_en_s <= false;
force_mc_s <= false;
en_int_v := true;
ack_int_s <= false;
cyc_v := to_integer(cyc_cnt_q);
-- determine type
t41x_type_v := opt_type_g = t400_opt_type_410_c;
t420_type_v := opt_type_g = t400_opt_type_420_c;
if icyc_en_i then
-- immediately increment program counter
-- this happens at two occasions:
-- a) right before new mnemonic becomes valid
-- b) before the second instruction cycle begins
pc_op_o <= PC_INC_PC;
end if;
if icyc_en_i and last_cycle_s then
-- update skip state when last instruction cycle ends
skip_op_o <= SKIP_UPDATE;
end if;
-- skip instruction execution
if not skip_i then
-- implement instruction control
case mnemonic_q is
-- Mnemonic ASC -------------------------------------------------------
when MN_ASC =>
if cyc_v = 1 then
alu_op_o <= ALU_ADD_C;
skip_op_o <= SKIP_CARRY;
end if;
-- Mnemonic ADD -------------------------------------------------------
when MN_ADD =>
if cyc_v = 1 then
alu_op_o <= ALU_ADD;
end if;
-- Mnemonic ADT -------------------------------------------------------
when MN_ADT =>
if cyc_v = 1 then
alu_op_o <= ALU_ADD_10;
end if;
-- Mnemonic AISC ------------------------------------------------------
when MN_AISC =>
dec_data_o(dw_range_t) <= ibyte1_q(dw_range_t);
if cyc_v = 1 then
alu_op_o <= ALU_ADD_DEC;
skip_op_o <= SKIP_CARRY;
end if;
-- Mnemonic CASC ------------------------------------------------------
when MN_CASC =>
case cyc_v is
when 0 =>
alu_op_o <= ALU_COMP;
when 1 =>
alu_op_o <= ALU_ADD_C;
skip_op_o <= SKIP_CARRY;
when others =>
null;
end case;
-- Mnemonic CLRA ------------------------------------------------------
when MN_CLRA =>
if cyc_v = 1 then
alu_op_o <= ALU_CLRA;
end if;
-- Mnemonic COMP ------------------------------------------------------
when MN_COMP =>
if cyc_v = 1 then
alu_op_o <= ALU_COMP;
end if;
-- Mnemonic NOP -------------------------------------------------------
when MN_NOP =>
-- do nothing
null;
-- Mnemonic C ---------------------------------------------------------
when MN_C =>
if cyc_v = 1 then
if ibyte1_q(4) = '1' then
alu_op_o <= ALU_RC;
else
alu_op_o <= ALU_SC;
end if;
end if;
-- Mnemonic XOR -------------------------------------------------------
when MN_XOR =>
if cyc_v = 1 then
alu_op_o <= ALU_XOR;
end if;
-- Mnemonic JID -------------------------------------------------------
when MN_JID =>
force_mc_s <= true;
en_int_v := false;
dec_data_o(byte_t'range) <= pm_data_i;
if cyc_v = 1 then
if not second_cyc_q then
-- first cycle: load PC from A and M
pc_op_o <= PC_LOAD_A_M;
else
-- second cycle: load PC from program memory
pc_op_o <= PC_LOAD_8;
end if;
end if;
if icyc_en_i and not second_cyc_q then
-- do not increment PC for second instruction cycle
pc_op_o <= PC_NONE;
end if;
-- Mnemonic JMP -------------------------------------------------------
when MN_JMP =>
en_int_v := false;
dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
if second_cyc_q and cyc_v = 1 then
pc_op_o <= PC_LOAD;
end if;
-- Mnemonic JP_JSRP ---------------------------------------------------
when MN_JP_JSRP =>
en_int_v := false;
-- universal decoder data
dec_data_o <= '0' & "01" & ibyte1_q(6 downto 0);
if cyc_v = 1 then
if pm_addr_i(9 downto 7) = "001" then
-- JP within pages 2 & 3
pc_op_o <= PC_LOAD_7;
elsif ibyte1_q(6) = '1' then
-- JP outside of pages 2 & 3
pc_op_o <= PC_LOAD_6;
else
-- JSRP to page 2
pc_op_o <= PC_LOAD;
stack_op_o <= STACK_PUSH;
end if;
end if;
-- Mnemonic JSR -------------------------------------------------------
when MN_JSR =>
en_int_v := false;
dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
if second_cyc_q and cyc_v = 1 then
pc_op_o <= PC_LOAD;
stack_op_o <= STACK_PUSH;
end if;
-- Mnemonic RET -------------------------------------------------------
when MN_RET =>
en_int_v := false;
if cyc_v = 1 then
pc_op_o <= PC_POP;
stack_op_o <= STACK_POP;
if t420_type_v then
-- always restore skip state in case this was an interrupt
skip_op_o <= SKIP_POP;
end if;
end if;
-- Mnemonic RETSK -----------------------------------------------------
when MN_RETSK =>
en_int_v := false;
if cyc_v = 1 then
pc_op_o <= PC_POP;
stack_op_o <= STACK_POP;
skip_op_o <= SKIP_NOW;
end if;
-- Mnemonic LD --------------------------------------------------------
when MN_LD =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_M;
b_op_o <= B_XOR_BR;
end if;
-- Mnemonic LDD_XAD ---------------------------------------------------
when MN_LDD_XAD =>
-- preload decoder data
dec_data_o(b_range_t) <= ibyte2_q(b_range_t);
if second_cyc_q then
case ibyte2_q(7 downto 6) is
-- LDD
when "00" =>
if not t41x_type_v then
case cyc_v is
when 1 =>
dmem_op_o <= DMEM_RDEC;
when 2 =>
alu_op_o <= ALU_LOAD_M;
when others =>
null;
end case;
end if;
-- XAD
when "10" =>
if not t41x_type_v or
unsigned(ibyte2_q(b_range_t)) = 63 then
case cyc_v is
when 1 =>
dmem_op_o <= DMEM_RDEC;
when 2 =>
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WDEC_SRC_A;
when others =>
null;
end case;
end if;
when others =>
null;
end case;
end if;
-- Mnemonic LQID ------------------------------------------------------
when MN_LQID =>
force_mc_s <= true;
en_int_v := false;
if not second_cyc_q then
-- first cycle: push PC and set PC from A/M,
-- read IOL from program memory
if cyc_v = 1 then
stack_op_o <= STACK_PUSH;
pc_op_o <= PC_LOAD_A_M;
end if;
if out_en_i then
io_l_op_o <= IOL_LOAD_PM;
end if;
else
if cyc_v = 1 then
-- second cycle: pop PC
stack_op_o <= STACK_POP;
pc_op_o <= PC_POP;
end if;
end if;
if icyc_en_i and not second_cyc_q then
-- do not increment PC for second instruction cycle
pc_op_o <= PC_NONE;
end if;
-- Mnemonic RMB -------------------------------------------------------
when MN_RMB =>
if cyc_v = 1 then
dmem_op_o <= DMEM_WB_RES_BIT;
-- select bit to be reset
case ibyte1_q(dw_range_t) is
when "1100" =>
dec_data_o(dw_range_t) <= "0001";
when "0101" =>
dec_data_o(dw_range_t) <= "0010";
when "0010" =>
dec_data_o(dw_range_t) <= "0100";
when "0011" =>
dec_data_o(dw_range_t) <= "1000";
when others =>
null;
end case;
end if;
-- Mnemonic SMB -------------------------------------------------------
when MN_SMB =>
if cyc_v = 1 then
dmem_op_o <= DMEM_WB_SET_BIT;
-- select bit to be set
case ibyte1_q(dw_range_t) is
when "1101" =>
dec_data_o(dw_range_t) <= "0001";
when "0111" =>
dec_data_o(dw_range_t) <= "0010";
when "0110" =>
dec_data_o(dw_range_t) <= "0100";
when "1011" =>
dec_data_o(dw_range_t) <= "1000";
when others =>
null;
end case;
end if;
-- Mnemonic STII ------------------------------------------------------
when MN_STII =>
dec_data_o(dw_range_t) <= ibyte1_q(dw_range_t);
if cyc_v = 1 then
dmem_op_o <= DMEM_WB_SRC_DEC;
b_op_o <= B_INC_BD;
end if;
-- Mnemonic X ---------------------------------------------------------
when MN_X =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WB_SRC_A;
b_op_o <= B_XOR_BR;
end if;
-- Mnemonic XDS -------------------------------------------------------
when MN_XDS =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
case cyc_v is
when 1 =>
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WB_SRC_A;
b_op_o <= B_DEC_BD;
when 2 =>
b_op_o <= B_XOR_BR;
skip_op_o <= SKIP_BD_UFLOW;
when others =>
null;
end case;
-- Mnemonic XIS -------------------------------------------------------
when MN_XIS =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
case cyc_v is
when 1 =>
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WB_SRC_A;
b_op_o <= B_INC_BD;
when 2 =>
b_op_o <= B_XOR_BR;
skip_op_o <= SKIP_BD_OFLOW;
when others =>
null;
end case;
-- Mnemonic CAB -------------------------------------------------------
when MN_CAB =>
if cyc_v = 1 then
b_op_o <= B_SET_BD;
end if;
-- Mnemonic CBA -------------------------------------------------------
when MN_CBA =>
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_BD;
end if;
-- Mnemonic LBI -------------------------------------------------------
when MN_LBI =>
is_lbi_o <= true;
en_int_v := false;
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
dec_data_o(bd_range_t) <= ibyte1_q(bd_range_t);
if cyc_v = 1 and not skip_lbi_i then
-- increment Bd by 1
b_op_o <= B_SET_B_INC;
skip_op_o <= SKIP_LBI;
end if;
-- Mnemonic XABR ------------------------------------------------------
when MN_XABR =>
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_BR;
b_op_o <= B_SET_BR;
end if;
-- Mnemonic SKC -------------------------------------------------------
when MN_SKC =>
if cyc_v = 1 then
skip_op_o <= SKIP_C;
end if;
-- Mnemonic SKE -------------------------------------------------------
when MN_SKE =>
if cyc_v = 1 then
skip_op_o <= SKIP_A_M;
end if;
-- Mnemonic SKMBZ -----------------------------------------------------
when MN_SKMBZ =>
if cyc_v = 1 then
skip_op_o <= SKIP_M_BIT;
-- select bit to be checked
case ibyte1_q is
when "00000001" =>
dec_data_o(dw_range_t) <= "0001";
when "00010001" =>
dec_data_o(dw_range_t) <= "0010";
when "00000011" =>
dec_data_o(dw_range_t) <= "0100";
when "00010011" =>
dec_data_o(dw_range_t) <= "1000";
when others =>
null;
end case;
end if;
-- Mnemonic SKT -------------------------------------------------------
when MN_SKT =>
if cyc_v = 1 then
skip_op_o <= SKIP_TIMER;
end if;
-- Mnemonic XAS -------------------------------------------------------
when MN_XAS =>
if out_en_i then
sio_op_o <= SIO_LOAD;
alu_op_o <= ALU_LOAD_SIO;
end if;
-- Mnemonic EXT -------------------------------------------------------
when MN_EXT =>
if second_cyc_q then
case ibyte2_q is
-- CAMQ
when "00111100" =>
if out_en_i then
io_l_op_o <= IOL_LOAD_AM;
end if;
-- CQMA
when "00101100" =>
if not t41x_type_v and in_en_i then
io_l_op_o <= IOL_OUTPUT_Q;
alu_op_o <= ALU_LOAD_Q;
dmem_op_o <= DMEM_WB_SRC_Q;
end if;
-- SKGZ
when "00100001" =>
if in_en_i then
skip_op_o <= SKIP_G_ZERO;
end if;
-- SKGBZ
when "00000001" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "0001";
end if;
when "00010001" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "0010";
end if;
when "00000011" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "0100";
end if;
when "00010011" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "1000";
end if;
-- ING
when "00101010" =>
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_G;
end if;
-- INL
when "00101110" =>
if in_en_i then
io_l_op_o <= IOL_OUTPUT_L;
alu_op_o <= ALU_LOAD_Q;
dmem_op_o <= DMEM_WB_SRC_Q;
end if;
-- ININ
when "00101000" =>
if not t41x_type_v and in_en_i then
alu_op_o <= ALU_LOAD_IN;
end if;
-- INIL
when "00101001" =>
if not t41x_type_v and in_en_i then
alu_op_o <= ALU_LOAD_IL;
io_in_op_o <= IOIN_INIL;
end if;
-- OBD
when "00111110" =>
if out_en_i then
io_d_op_o <= IOD_LOAD;
end if;
-- OMG
when "00111010" =>
if out_en_i then
io_g_op_o <= IOG_LOAD_M;
end if;
-- multiple codes
when others =>
-- apply default decoder output, largest required vector
dec_data_o(b_range_t) <= ibyte2_q(b_range_t);
-- LBI
if ibyte2_q(7 downto 6) = "10" and not t41x_type_v then
is_lbi_o <= true;
en_int_v := false;
if cyc_v > 0 and not skip_lbi_i then
b_op_o <= B_SET_B;
skip_op_o <= SKIP_LBI;
end if;
end if;
-- LEI
if ibyte2_q(7 downto 4) = "0110" and in_en_i then
-- dec_data_o applied by default
set_en_s <= true;
-- acknowledge pending interrupt when EN(1) is not
-- enabled - will clear them until interrupts are
-- enabled with EN(1) = '1'
if en_q(1) = '0' then
io_in_op_o <= IOIN_INTACK;
end if;
end if;
-- OGI
if ibyte2_q(7 downto 4) = "0101" and out_en_i and
not t41x_type_v then
-- dec_data_o applied by default
io_g_op_o <= IOG_LOAD_DEC;
end if;
end case;
end if;
when others =>
null;
end case;
end if;
-- Interrupt handling -----------------------------------------------------
if t420_type_v and
en_q(1) = '1' and int_i and en_int_v then
if last_cycle_s then
if cyc_v = 1 then
stack_op_o <= STACK_PUSH;
end if;
if icyc_en_i then
ack_int_s <= true;
io_in_op_o <= IOIN_INTACK;
pc_op_o <= PC_INT;
-- push skip state that was determined by current instruction
-- and will be valid for the next instruction which is delayed
-- by the interrupt
skip_op_o <= SKIP_PUSH;
end if;
end if;
end if;
end process decoder_ctrl;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
en_o <= en_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_decoder.vhd,v $
-- Revision 1.6 2006/06/05 14:20:34 arniml
-- interface comments added
--
-- Revision 1.5 2006/05/28 15:32:14 arniml
-- execute virtual NOP at location 0x0ff when vectoring to interrupt routine
--
-- Revision 1.4 2006/05/27 19:14:18 arniml
-- interrupt functionality added
--
-- Revision 1.3 2006/05/22 00:02:36 arniml
-- instructions ININ and INIL implemented
--
-- Revision 1.2 2006/05/07 02:24:16 arniml
-- fix sensitivity list
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Data memory controller.
--
-- $Id: t400_dmem_ctrl-c.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_dmem_ctrl_rtl_c0 of t400_dmem_ctrl is
for rtl
end for;
end t400_dmem_ctrl_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_dmem_ctrl-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Data memory controller.
--
-- $Id: t400_dmem_ctrl.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_dmem_ctrl is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ------------------------------------------------------
dmem_op_i : in dmem_op_t;
b_op_i : in b_op_t;
dec_data_i : in dec_data_t;
a_i : in dw_t;
q_high_i : in dw_t;
b_o : out b_t;
-- Data Memory Interface --------------------------------------------------
dm_addr_o : out dm_addr_t;
dm_data_i : in dw_t;
dm_data_o : out dw_t;
dm_we_o : out std_logic
);
end t400_dmem_ctrl;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_dmem_ctrl is
signal br_q : unsigned(br_range_t);
signal bd_q : unsigned(bd_range_t);
begin
-----------------------------------------------------------------------------
-- Process b_reg
--
-- Purpose:
-- Implements the B register.
--
b_reg: process (ck_i, por_i)
begin
if por_i then
br_q <= (others => '0');
bd_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
br_q <= (others => '0');
bd_q <= (others => '0');
elsif ck_en_i then
case b_op_i is
-- Set Bd from accumulator ------------------------------------------
when B_SET_BD =>
bd_q <= unsigned(a_i);
-- Set Br from accumulator ------------------------------------------
when B_SET_BR =>
br_q <= unsigned(a_i(1 downto 0));
-- Set Br and Bd from decoder data ----------------------------------
when B_SET_B =>
br_q <= unsigned(dec_data_i(br_range_t));
bd_q <= unsigned(dec_data_i(bd_range_t));
-- Set Br and Bd from decoder data, increment value for Bd ----------
when B_SET_B_INC =>
br_q <= unsigned(dec_data_i(br_range_t));
bd_q <= unsigned(dec_data_i(bd_range_t)) + 1;
-- XOR Br with decoder data -----------------------------------------
when B_XOR_BR =>
br_q <= br_q xor unsigned(dec_data_i(br_range_t));
-- Increment Bd -----------------------------------------------------
when B_INC_BD =>
bd_q <= bd_q + 1;
-- Increment Bd -----------------------------------------------------
when B_DEC_BD =>
bd_q <= bd_q - 1;
when others =>
null;
end case;
end if;
end if;
end process b_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process data_mux
--
-- Purpose:
-- Multiplexes the data for writing to the memory.
--
data_mux: process (dmem_op_i,
br_q, bd_q,
a_i,
q_high_i,
dec_data_i,
dm_data_i,
ck_en_i)
variable dm_addr_v : dm_addr_t;
variable dm_data_v : dw_t;
variable dm_we_v : std_logic;
variable bd_v : std_logic_vector(2 downto 0);
begin
-- default assignment
dm_addr_v(br_range_t) := std_logic_vector(br_q);
dm_addr_v(bd_range_t) := std_logic_vector(bd_q);
dm_data_v := (others => '0');
dm_we_v := '0';
case dmem_op_i is
-- Read data memory, indexed by B ---------------------------------------
when DMEM_RB =>
null;
-- Write data memory, indexed by B, source is Q -------------------------
when DMEM_WB_SRC_Q =>
dm_we_v := '1';
dm_data_v := q_high_i;
-- Write data memory, indexed by B, source is decoder data --------------
when DMEM_WB_SRC_DEC =>
dm_we_v := '1';
dm_data_v := dec_data_i(bd_range_t);
-- Write data memory, indexed by B, source is accumulator ---------------
when DMEM_WB_SRC_A =>
dm_we_v := '1';
dm_data_v := a_i;
-- Read data memory, indexed by decoder data ----------------------------
when DMEM_RDEC =>
dm_addr_v := dec_data_i(br_range_t'high downto 0);
-- Write data memory, indexed by decoder data, source is accumulator ----
when DMEM_WDEC_SRC_A =>
dm_we_v := '1';
dm_addr_v := dec_data_i(br_range_t'high downto 0);
dm_data_v := a_i;
-- Write data memory, indexed by B, set bit -----------------------------
when DMEM_WB_SET_BIT =>
dm_we_v := '1';
dm_data_v := dm_data_i or dec_data_i(dw_range_t);
-- Write data memory, indexed by B, reset bit ---------------------------
when DMEM_WB_RES_BIT =>
dm_we_v := '1';
dm_data_v := dm_data_i and not dec_data_i(dw_range_t);
when others =>
null;
end case;
-- adjust address vector for 41xL family members
if opt_type_g = t400_opt_type_410_c then
dm_addr_v := '0' & dm_addr_v(br_range_t) &
dm_addr_v(bd_range_t'high-1 downto 0);
end if;
dm_addr_o <= dm_addr_v;
if ck_en_i then
dm_we_o <= dm_we_v;
else
dm_we_o <= '0';
end if;
dm_data_o <= dm_data_v;
end process data_mux;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
b_o(br_range_t) <= std_logic_vector(br_q);
b_o(bd_range_t) <= std_logic_vector(bd_q);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_dmem_ctrl.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The D port controller.
--
-- $Id: t400_io_d-c.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_io_d_rtl_c0 of t400_io_d is
for rtl
end for;
end t400_io_d_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_io_d-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The D port controller.
--
-- $Id: t400_io_d.vhd,v 1.2 2006/05/07 02:24:16 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_io_d is
generic (
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in io_d_op_t;
bd_i : in bd_t;
-- Port D Interface -------------------------------------------------------
io_d_o : out dw_t;
io_d_en_o : out dw_t
);
end t400_io_d;
use work.t400_io_pack.all;
architecture rtl of t400_io_d is
signal d_q : dw_t;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Process d_reg
--
-- Purpose:
-- Implements the D output register.
--
d_reg: process (ck_i, por_i)
begin
if por_i then
d_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
d_q <= (others => '0');
elsif ck_en_i then
if op_i = IOD_LOAD then
d_q <= bd_i;
end if;
end if;
end if;
end process d_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process out_driver
--
-- Purpose:
-- Implements the output driver data and enable.
--
out_driver: process (d_q,
vdd_s)
begin
-- bit 3
io_d_o(3) <= io_out_f(dat => d_q(3),
opt => opt_out_type_3_g);
io_d_en_o(3) <= io_en_f (en => vdd_s, dat => d_q(3),
opt => opt_out_type_3_g);
-- bit 2
io_d_o(2) <= io_out_f(dat => d_q(2),
opt => opt_out_type_2_g);
io_d_en_o(2) <= io_en_f (en => vdd_s, dat => d_q(2),
opt => opt_out_type_2_g);
-- bit 1
io_d_o(1) <= io_out_f(dat => d_q(1),
opt => opt_out_type_1_g);
io_d_en_o(1) <= io_en_f (en => vdd_s, dat => d_q(1),
opt => opt_out_type_1_g);
-- bit 0
io_d_o(0) <= io_out_f(dat => d_q(0),
opt => opt_out_type_0_g);
io_d_en_o(0) <= io_en_f (en => vdd_s, dat => d_q(0),
opt => opt_out_type_0_g);
end process out_driver;
--
-----------------------------------------------------------------------------
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_io_d.vhd,v $
-- Revision 1.2 2006/05/07 02:24:16 arniml
-- fix sensitivity list
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The G port controller.
--
-- $Id: t400_io_g-c.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_io_g_rtl_c0 of t400_io_g is
for rtl
end for;
end t400_io_g_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_io_g-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The G port controller.
--
-- $Id: t400_io_g.vhd,v 1.3 2006/06/05 20:32:34 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_io_g is
generic (
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in io_g_op_t;
m_i : in dw_t;
dec_data_i : in dec_data_t;
cs_n_i : in std_logic;
wr_n_i : in std_logic;
-- Port G Interface -------------------------------------------------------
io_g_o : out dw_t;
io_g_en_o : out dw_t
);
end t400_io_g;
use work.t400_io_pack.all;
architecture rtl of t400_io_g is
signal g_q : dw_t;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Process g_reg
--
-- Purpose:
-- Implements the G output register.
--
g_reg: process (ck_i, por_i)
begin
if por_i then
g_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
g_q <= (others => '0');
elsif ck_en_i then
case op_i is
when IOG_LOAD_M =>
g_q <= m_i;
when IOG_LOAD_DEC =>
g_q <= dec_data_i(dw_range_t);
when others =>
null;
end case;
end if;
-- reset G(0) in MICROBUS operation upon write
if opt_microbus_g = t400_opt_microbus_c and
cs_n_i = '0' and wr_n_i = '0' then
g_q(0) <= '0';
end if;
end if;
end process g_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process out_driver
--
-- Purpose:
-- Implements the output driver data and enable.
--
out_driver: process (g_q,
vdd_s)
begin
-- bit 3
io_g_o(3) <= io_out_f(dat => g_q(3),
opt => opt_out_type_3_g);
io_g_en_o(3) <= io_en_f (en => vdd_s, dat => g_q(3),
opt => opt_out_type_3_g);
-- bit 2
io_g_o(2) <= io_out_f(dat => g_q(2),
opt => opt_out_type_2_g);
io_g_en_o(2) <= io_en_f (en => vdd_s, dat => g_q(2),
opt => opt_out_type_2_g);
-- bit 1
io_g_o(1) <= io_out_f(dat => g_q(1),
opt => opt_out_type_1_g);
io_g_en_o(1) <= io_en_f (en => vdd_s, dat => g_q(1),
opt => opt_out_type_1_g);
-- bit 0
io_g_o(0) <= io_out_f(dat => g_q(0),
opt => opt_out_type_0_g);
io_g_en_o(0) <= io_en_f (en => vdd_s, dat => g_q(0),
opt => opt_out_type_0_g);
end process out_driver;
--
-----------------------------------------------------------------------------
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_io_g.vhd,v $
-- Revision 1.3 2006/06/05 20:32:34 arniml
-- reset G(0) upon write access in microbus mode
--
-- Revision 1.2 2006/05/07 02:24:16 arniml
-- fix sensitivity list
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The IN port controller.
--
-- $Id: t400_io_in-c.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_io_in_rtl_c0 of t400_io_in is
for rtl
end for;
end t400_io_in_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_io_in-c.vhd,v $
-- Revision 1.1.1.1 2006/06/10 17:50:15 arnim
-- copied from opencores.org repository, pre-1.0 release on 10-Jun-2006
--
-- Revision 1.1 2006/05/22 00:00:55 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The IN port controller.
--
-- $Id: t400_io_in.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.all;
entity t400_io_in is
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
icyc_en_i : in boolean;
in_en_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in io_in_op_t;
en1_i : in std_logic;
-- Port Interface ---------------------------------------------------------
io_in_i : in dw_t;
in_o : out dw_t;
int_o : out boolean
);
end t400_io_in;
architecture rtl of t400_io_in is
constant idx_in3_c : natural := 2;
constant idx_in0_c : natural := 1;
constant idx_int_c : natural := 0;
type neg_edge_t is array (natural range 1 downto 0) of
std_logic_vector(2 downto 0);
signal neg_edge_q : neg_edge_t;
signal neg_edge_s : std_logic_vector(2 downto 0);
signal il_q : std_logic_vector(1 downto 0);
signal int_q,
int_icyc_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements.
--
seq: process (ck_i, por_i)
variable neg_edge_v : std_logic_vector(2 downto 0);
begin
if por_i then
neg_edge_q <= (others => (others => '0'));
il_q <= (others => '0');
int_q <= false;
int_icyc_q <= false;
elsif ck_i'event and ck_i = '1' then
-- negative edge detector filp-flops ------------------------------------
neg_edge_v(idx_in3_c) := to_X01(io_in_i(3));
neg_edge_v(idx_in0_c) := to_X01(io_in_i(0));
neg_edge_v(idx_int_c) := to_X01(io_in_i(1));
if in_en_i then
neg_edge_q(0) <= neg_edge_v;
neg_edge_q(1) <= neg_edge_q(0) or neg_edge_v;
end if;
-- IL latches -----------------------------------------------------------
if in_en_i then
if neg_edge_q(1)(idx_in3_c) = '1' and
((neg_edge_q(0)(idx_in3_c) or neg_edge_v(idx_in3_c)) = '0') then
il_q(1) <= '1';
end if;
if neg_edge_q(1)(idx_in0_c) = '1' and
((neg_edge_q(0)(idx_in0_c) or neg_edge_v(idx_in0_c)) = '0') then
il_q(0) <= '1';
end if;
end if;
-- Interrupt trigger ----------------------------------------------------
if in_en_i then
if neg_edge_q(1)(idx_int_c) = '1' and
((neg_edge_q(0)(idx_int_c) or neg_edge_v(idx_int_c)) = '0') then
int_q <= true;
end if;
end if;
if icyc_en_i then
-- delay interrupt request until end of current instruction
-- this ensures that the interrupt is valid for a full instruction
-- (i.e. the next one)
int_icyc_q <= int_q;
end if;
if ck_en_i then
if op_i = IOIN_INIL then
il_q <= (others => '0');
end if;
if op_i = IOIN_INTACK then
int_q <= false;
int_icyc_q <= false;
end if;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
in_o <= il_q(1) & "00" & il_q(0)
when op_i = IOIN_INIL else
io_in_i;
int_o <= int_icyc_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_io_in.vhd,v $
-- Revision 1.1.1.1 2006/06/10 17:50:15 arnim
-- copied from opencores.org repository, pre-1.0 release on 10-Jun-2006
--
-- Revision 1.3 2006/05/27 19:14:18 arniml
-- interrupt functionality added
--
-- Revision 1.2 2006/05/23 01:13:28 arniml
-- + reset neg_edge flip-flops to '1'
-- -> after por, a 1-to-0 edge is required to trigger the latches initially
-- + use to_X01
--
-- Revision 1.1 2006/05/22 00:00:55 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The L port controller.
--
-- $Id: t400_io_l-c.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_io_l_rtl_c0 of t400_io_l is
for rtl
end for;
end t400_io_l_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_io_l-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The L port controller.
--
-- $Id: t400_io_l.vhd,v 1.4 2006/06/05 20:33:24 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_io_l is
generic (
opt_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
in_en_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in io_l_op_t;
en2_i : in std_logic;
m_i : in dw_t;
a_i : in dw_t;
pm_data_i : in byte_t;
q_o : out byte_t;
-- Microbus Interface -----------------------------------------------------
cs_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
-- Port L Interface -------------------------------------------------------
io_l_i : in byte_t;
io_l_o : out byte_t;
io_l_en_o : out byte_t
);
end t400_io_l;
use work.t400_io_pack.all;
architecture rtl of t400_io_l is
signal q_q : byte_t;
signal en2_s : std_logic;
begin
-----------------------------------------------------------------------------
-- Process q_reg
--
-- Purpose:
-- Implements the Q register.
--
q_reg: process (ck_i, por_i)
begin
if por_i then
q_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if ck_en_i then
case op_i is
-- Load Q from accumulator and data memory --------------------------
when IOL_LOAD_AM =>
q_q(7 downto 4) <= a_i;
q_q(3 downto 0) <= m_i;
-- Load Q from program memory ---------------------------------------
when IOL_LOAD_PM =>
q_q <= pm_data_i;
when others =>
null;
end case;
end if;
-- Microbus functionality
if opt_microbus_g = t400_opt_microbus_c and
cs_n_i = '0' and wr_n_i = '0' then
q_q <= to_X01(io_l_i);
end if;
end if;
end process q_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Multiplexer providing read data to the system.
-----------------------------------------------------------------------------
q_o <= to_X01(io_l_i)
when op_i = IOL_OUTPUT_L else
q_q;
-----------------------------------------------------------------------------
-- Dedicated output enable when in Microbus mode
-----------------------------------------------------------------------------
en2_s <= cs_n_i nor rd_n_i
when opt_microbus_g = t400_opt_microbus_c else
en2_i;
-----------------------------------------------------------------------------
-- Process out_driver
--
-- Purpose:
-- Implements the output driver data and enable.
--
out_driver: process (en2_s,
q_q)
begin
-- bit 7
io_l_o(7) <= io_out_f(dat => q_q(7),
opt => opt_out_type_7_g);
io_l_en_o(7) <= io_en_f (en => en2_s, dat => q_q(7),
opt => opt_out_type_7_g);
-- bit 6
io_l_o(6) <= io_out_f(dat => q_q(6),
opt => opt_out_type_6_g);
io_l_en_o(6) <= io_en_f (en => en2_s, dat => q_q(6),
opt => opt_out_type_6_g);
-- bit 5
io_l_o(5) <= io_out_f(dat => q_q(5),
opt => opt_out_type_5_g);
io_l_en_o(5) <= io_en_f (en => en2_s, dat => q_q(5),
opt => opt_out_type_5_g);
-- bit 4
io_l_o(4) <= io_out_f(dat => q_q(4),
opt => opt_out_type_4_g);
io_l_en_o(4) <= io_en_f (en => en2_s, dat => q_q(4),
opt => opt_out_type_4_g);
-- bit 3
io_l_o(3) <= io_out_f(dat => q_q(3),
opt => opt_out_type_3_g);
io_l_en_o(3) <= io_en_f (en => en2_s, dat => q_q(3),
opt => opt_out_type_3_g);
-- bit 2
io_l_o(2) <= io_out_f(dat => q_q(2),
opt => opt_out_type_2_g);
io_l_en_o(2) <= io_en_f (en => en2_s, dat => q_q(2),
opt => opt_out_type_2_g);
-- bit 1
io_l_o(1) <= io_out_f(dat => q_q(1),
opt => opt_out_type_1_g);
io_l_en_o(1) <= io_en_f (en => en2_s, dat => q_q(1),
opt => opt_out_type_1_g);
-- bit 0
io_l_o(0) <= io_out_f(dat => q_q(0),
opt => opt_out_type_0_g);
io_l_en_o(0) <= io_en_f (en => en2_s, dat => q_q(0),
opt => opt_out_type_0_g);
end process out_driver;
--
-----------------------------------------------------------------------------
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_io_l.vhd,v $
-- Revision 1.4 2006/06/05 20:33:24 arniml
-- latch Q independently of in_en
--
-- Revision 1.3 2006/06/05 14:21:21 arniml
-- latch io_l_i upon input enable trigger
--
-- Revision 1.2 2006/05/23 01:14:28 arniml
-- use to_X01 for primary input bus
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- $Id: t400_io_pack-p.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package t400_io_pack is
function io_out_f(dat : in std_logic;
opt : in integer) return std_logic;
function io_en_f (en : in std_logic;
dat : in std_logic;
opt : in integer) return std_logic;
end t400_io_pack;
use work.t400_opt_pack.all;
package body t400_io_pack is
function io_out_f(dat : in std_logic;
opt : in integer) return std_logic is
variable result_v : std_logic;
begin
result_v := '-';
case opt is
-- Open drain type output drivers ---------------------------------------
when t400_opt_out_type_od_c =>
result_v := '0';
-- Push/pull type output drivers ----------------------------------------
when t400_opt_out_type_std_c |
t400_opt_out_type_led_c |
t400_opt_out_type_pp_c =>
result_v := dat;
when others =>
null;
end case;
return result_v;
end io_out_f;
function io_en_f (en : in std_logic;
dat : in std_logic;
opt : in integer) return std_logic is
variable result_v : std_logic;
begin
result_v := '0';
case opt is
-- Open drain type output drivers ---------------------------------------
when t400_opt_out_type_od_c =>
if en = '1' and dat = '0' then
result_v := '1';
end if;
-- Push/pull type output drivers ----------------------------------------
when t400_opt_out_type_std_c |
t400_opt_out_type_led_c |
t400_opt_out_type_pp_c =>
result_v := en;
when others =>
null;
end case;
return result_v;
end io_en_f;
end t400_io_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_io_pack-p.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The opcode decoder table.
-- Maps the binary opcodes to the mnemonic type.
--
-- $Id: t400_opc_table-c.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_opc_table_rtl_c0 of t400_opc_table is
for rtl
end for;
end t400_opc_table_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_opc_table-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The opcode decoder table.
-- Maps the binary opcodes to the mnemonic type.
--
-- $Id: t400_opc_table.vhd,v 1.1.1.1 2006/05/06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_opc_table is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
opcode_i : in byte_t;
mnemonic_o : out mnemonic_t;
multi_byte_o : out boolean
);
end t400_opc_table;
architecture rtl of t400_opc_table is
begin
-----------------------------------------------------------------------------
-- Process opc_decode
--
-- Purpose:
-- Decodes the opcode to the set of mnemonics.
--
opc_decode: process (opcode_i)
variable t41x_type_v : boolean;
begin
-- default assignment
mnemonic_o <= MN_NOP;
multi_byte_o <= false;
-- determine type
t41x_type_v := opt_type_g = t400_opt_type_410_c;
case opcode_i is
-- Mnemonic ASC----------------------------------------------------------
when "00110000" =>
mnemonic_o <= MN_ASC;
-- Mnemonic ADD ---------------------------------------------------------
when "00110001" =>
mnemonic_o <= MN_ADD;
-- Mnemonic ADT ---------------------------------------------------------
when "01001010" =>
if not t41x_type_v then
mnemonic_o <= MN_ADT;
end if;
-- Mnemonic AISC --------------------------------------------------------
when "01010001" | "01010010" | "01010011" |
"01010100" | "01010101" | "01010110" | "01010111" |
"01011000" | "01011001" | "01011010" | "01011011" |
"01011100" | "01011101" | "01011110" | "01011111" =>
mnemonic_o <= MN_AISC;
-- Mnemonic CASC --------------------------------------------------------
when "00010000" =>
if not t41x_type_v then
mnemonic_o <= MN_CASC;
end if;
-- Mnemonic CLRA --------------------------------------------------------
when "00000000" =>
mnemonic_o <= MN_CLRA;
-- Mnemonic COMP --------------------------------------------------------
when "01000000" =>
mnemonic_o <= MN_COMP;
-- Mnemonic NOP ---------------------------------------------------------
when "01000100" =>
mnemonic_o <= MN_NOP;
-- Mnemonic C -----------------------------------------------------------
when "00110010" | -- RC
"00100010" => -- SC
mnemonic_o <= MN_C;
-- Mnemonic XOR ---------------------------------------------------------
when "00000010" =>
mnemonic_o <= MN_XOR;
-- Mnemonic JID ---------------------------------------------------------
when "11111111" =>
mnemonic_o <= MN_JID;
-- Mnemonic JMP ---------------------------------------------------------
when "01100000" | "01100001" | "01100010" | "01100011" =>
mnemonic_o <= MN_JMP;
multi_byte_o <= true;
-- Mnemonic JP_JSRP -----------------------------------------------------
when "10000000" | "10000001" | "10000010" | "10000011" |
"10000100" | "10000101" | "10000110" | "10000111" |
"10001000" | "10001001" | "10001010" | "10001011" |
"10001100" | "10001101" | "10001110" | "10001111" |
"10010000" | "10010001" | "10010010" | "10010011" |
"10010100" | "10010101" | "10010110" | "10010111" |
"10011000" | "10011001" | "10011010" | "10011011" |
"10011100" | "10011101" | "10011110" | "10011111" |
"10100000" | "10100001" | "10100010" | "10100011" |
"10100100" | "10100101" | "10100110" | "10100111" |
"10101000" | "10101001" | "10101010" | "10101011" |
"10101100" | "10101101" | "10101110" | "10101111" |
"10110000" | "10110001" | "10110010" | "10110011" |
"10110100" | "10110101" | "10110110" | "10110111" |
"10111000" | "10111001" | "10111010" | "10111011" |
"10111100" | "10111101" | "10111110" |
"11000000" | "11000001" | "11000010" | "11000011" |
"11000100" | "11000101" | "11000110" | "11000111" |
"11001000" | "11001001" | "11001010" | "11001011" |
"11001100" | "11001101" | "11001110" | "11001111" |
"11010000" | "11010001" | "11010010" | "11010011" |
"11010100" | "11010101" | "11010110" | "11010111" |
"11011000" | "11011001" | "11011010" | "11011011" |
"11011100" | "11011101" | "11011110" | "11011111" |
"11100000" | "11100001" | "11100010" | "11100011" |
"11100100" | "11100101" | "11100110" | "11100111" |
"11101000" | "11101001" | "11101010" | "11101011" |
"11101100" | "11101101" | "11101110" | "11101111" |
"11110000" | "11110001" | "11110010" | "11110011" |
"11110100" | "11110101" | "11110110" | "11110111" |
"11111000" | "11111001" | "11111010" | "11111011" |
"11111100" | "11111101" | "11111110" =>
mnemonic_o <= MN_JP_JSRP;
-- Mnemonic JSR ---------------------------------------------------------
when "01101000" | "01101001" | "01101010" | "01101011" =>
mnemonic_o <= MN_JSR;
multi_byte_o <= true;
-- Mnemonic RET ---------------------------------------------------------
when "01001000" =>
mnemonic_o <= MN_RET;
-- Mnemonic RETSK -------------------------------------------------------
when "01001001" =>
mnemonic_o <= MN_RETSK;
-- Mnemonic LD ----------------------------------------------------------
when "00000101" | "00010101" | "00100101" | "00110101" =>
mnemonic_o <= MN_LD;
-- Mnemonic LDD_XAD -----------------------------------------------------
when "00100011" =>
mnemonic_o <= MN_LDD_XAD;
multi_byte_o <= true;
-- Mnemonic LQID --------------------------------------------------------
when "10111111" =>
mnemonic_o <= MN_LQID;
-- Mnemonic RMB ---------------------------------------------------------
when "01001100" | "01000101" | "01000010" | "01000011" =>
mnemonic_o <= MN_RMB;
-- Mnemonic SMB ---------------------------------------------------------
when "01001101" | "01000111" | "01000110" | "01001011" =>
mnemonic_o <= MN_SMB;
-- Mnemonic STII --------------------------------------------------------
when "01110000" | "01110001" | "01110010" | "01110011" |
"01110100" | "01110101" | "01110110" | "01110111" |
"01111000" | "01111001" | "01111010" | "01111011" |
"01111100" | "01111101" | "01111110" | "01111111" =>
mnemonic_o <= MN_STII;
-- Mnemonic X -----------------------------------------------------------
when "00000110" | "00010110" | "00100110" | "00110110" =>
mnemonic_o <= MN_X;
-- Mnemonic XDS ---------------------------------------------------------
when "00000111" | "00010111" | "00100111" | "00110111" =>
mnemonic_o <= MN_XDS;
-- Mnemonic XIS ---------------------------------------------------------
when "00000100" | "00010100" | "00100100" | "00110100" =>
mnemonic_o <= MN_XIS;
-- Mnemonic CAB ---------------------------------------------------------
when "01010000" =>
mnemonic_o <= MN_CAB;
-- Mnemonic CBA ---------------------------------------------------------
when "01001110" =>
mnemonic_o <= MN_CBA;
-- Mnemonic LBI ---------------------------------------------------------
when "00001000" | "00001001" | "00001010" | "00001011" |
"00001100" | "00001101" | "00001110" | "00001111" |
"00011000" | "00011001" | "00011010" | "00011011" |
"00011100" | "00011101" | "00011110" | "00011111" |
"00101000" | "00101001" | "00101010" | "00101011" |
"00101100" | "00101101" | "00101110" | "00101111" |
"00111000" | "00111001" | "00111010" | "00111011" |
"00111100" | "00111101" | "00111110" | "00111111" =>
mnemonic_o <= MN_LBI;
-- Mnemonic XABR --------------------------------------------------------
when "00010010" =>
if not t41x_type_v then
mnemonic_o <= MN_XABR;
end if;
-- Mnemonic SKC ---------------------------------------------------------
when "00100000" =>
mnemonic_o <= MN_SKC;
-- Mnemonic SKE ---------------------------------------------------------
when "00100001" =>
mnemonic_o <= MN_SKE;
-- Mnemonic SKMBZ -------------------------------------------------------
when "00000001" | "00010001" | "00000011" | "00010011" =>
mnemonic_o <= MN_SKMBZ;
-- Mnemonic SKT ---------------------------------------------------------
when "01000001" =>
if not t41x_type_v then
mnemonic_o <= MN_SKT;
end if;
-- Mnemonic XAS ---------------------------------------------------------
when "01001111" =>
mnemonic_o <= MN_XAS;
-- Mnemonic EXT ---------------------------------------------------------
when "00110011" =>
mnemonic_o <= MN_EXT;
multi_byte_o <= true;
when others =>
null;
end case;
end process opc_decode;
--
-----------------------------------------------------------------------------
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_opc_table.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- $Id: t400_opt_pack-p.vhd,v 1.1.1.1 2006/05/06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
package t400_opt_pack is
-- Chip type option ---------------------------------------------------------
constant t400_opt_type_420_c : integer := 0;
constant t400_opt_type_421_c : integer := 1;
constant t400_opt_type_410_c : integer := 2;
-- Clock divider option -----------------------------------------------------
constant t400_opt_ck_div_32_c : integer := 3;
constant t400_opt_ck_div_16_c : integer := 2;
constant t400_opt_ck_div_8_c : integer := 1;
constant t400_opt_ck_div_4_c : integer := 0;
-- CKO pin function option --------------------------------------------------
constant t400_opt_cko_crystal_c : integer := 0;
constant t400_opt_cko_gpi_c : integer := 1;
-- Output type option -------------------------------------------------------
constant t400_opt_out_type_std_c : integer := 0;
constant t400_opt_out_type_od_c : integer := 1;
constant t400_opt_out_type_led_c : integer := 2;
constant t400_opt_out_type_pp_c : integer := 3;
-- Microbus option ----------------------------------------------------------
constant t400_opt_no_microbus_c : integer := 0;
constant t400_opt_microbus_c : integer := 1;
end t400_opt_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_opt_pack-p.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- $Id: t400_pack-p.vhd,v 1.3 2006/05/27 19:16:52 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package t400_pack is
-- Byte ---------------------------------------------------------------------
subtype byte_t is std_logic_vector(7 downto 0);
-- Data word ----------------------------------------------------------------
subtype dw_t is std_logic_vector(3 downto 0);
-- Misc ranges --------------------------------------------------------------
subtype dw_range_t is natural range dw_t'range;
subtype b_range_t is natural range 5 downto 0;
subtype br_range_t is natural range 5 downto 4;
subtype bd_range_t is natural range 3 downto 0;
-- B address ----------------------------------------------------------------
subtype b_t is std_logic_vector(b_range_t);
subtype br_t is std_logic_vector(br_range_t);
subtype bd_t is std_logic_vector(bd_range_t);
-- Program counter ----------------------------------------------------------
subtype pc_t is unsigned(9 downto 0);
-- Data memory address vector -----------------------------------------------
subtype dm_addr_t is std_logic_vector(5 downto 0);
-- Decoder data -------------------------------------------------------------
subtype dec_data_t is std_logic_vector(pc_t'range);
-- Program counter operations -----------------------------------------------
type pc_op_t is (PC_NONE,
PC_INC_PC,
PC_LOAD_6, PC_LOAD_7, PC_LOAD_8, PC_LOAD,
PC_POP,
PC_LOAD_A_M,
PC_INT);
-- Data memory controller operations ----------------------------------------
type dmem_op_t is (DMEM_RB,
DMEM_WB_SRC_Q, DMEM_WB_SRC_DEC, DMEM_WB_SRC_A,
DMEM_RDEC,
DMEM_WB_SET_BIT, DMEM_WB_RES_BIT,
DMEM_WDEC_SRC_A);
type b_op_t is (B_NONE,
B_SET_BD, B_SET_BR,
B_SET_B, B_SET_B_INC,
B_XOR_BR,
B_INC_BD,
B_DEC_BD);
-- Stack operations ---------------------------------------------------------
type stack_op_t is (STACK_NONE,
STACK_PUSH,
STACK_POP);
-- ALU operations -----------------------------------------------------------
type alu_op_t is (ALU_NONE,
ALU_CLRA,
ALU_LOAD_M,
ALU_LOAD_Q, ALU_LOAD_G, ALU_LOAD_IN, ALU_LOAD_IL,
ALU_LOAD_BR, ALU_LOAD_BD,
ALU_LOAD_SIO,
ALU_ADD, ALU_ADD_10, ALU_ADD_C, ALU_ADD_DEC,
ALU_COMP,
ALU_RC, ALU_SC,
ALU_XOR);
-- Skip operations ----------------------------------------------------------
type skip_op_t is (SKIP_NONE,
SKIP_UPDATE,
SKIP_NOW,
SKIP_CARRY, SKIP_C,
SKIP_BD_UFLOW, SKIP_BD_OFLOW,
SKIP_LBI,
SKIP_A_M,
SKIP_G_ZERO, SKIP_G_BIT,
SKIP_M_BIT,
SKIP_TIMER,
SKIP_PUSH, SKIP_POP);
-- IO L port operations -----------------------------------------------------
type io_l_op_t is (IOL_NONE,
IOL_LOAD_AM, IOL_LOAD_PM,
IOL_OUTPUT_L,
IOL_OUTPUT_Q);
-- IO D port operations -----------------------------------------------------
type io_d_op_t is (IOD_NONE,
IOD_LOAD);
-- IO G port operations -----------------------------------------------------
type io_g_op_t is (IOG_NONE,
IOG_LOAD_M,
IOG_LOAD_DEC);
-- IO IN port operations ----------------------------------------------------
type io_in_op_t is (IOIN_NONE,
IOIN_INIL,
IOIN_INTACK);
-- SIO operations -----------------------------------------------------------
type sio_op_t is (SIO_NONE,
SIO_LOAD);
-- Mnemonics ----------------------------------------------------------------
type mnemonic_t is (-- Arithmetic instructions
MN_ASC,
MN_ADD,
MN_ADT,
MN_AISC,
MN_CASC,
MN_CLRA,
MN_COMP,
MN_NOP,
MN_C,
MN_XOR,
-- Transfer of control instructions
MN_JID,
MN_JMP,
MN_JP_JSRP,
MN_JSR,
MN_RET,
MN_RETSK,
-- Memory reference instructions
MN_LD,
MN_LDD_XAD,
MN_LQID,
MN_RMB,
MN_SMB,
MN_STII,
MN_X,
MN_XDS,
MN_XIS,
-- Register reference instructions
MN_CAB,
MN_CBA,
MN_LBI,
MN_XABR,
-- Test instructions
MN_SKC,
MN_SKE,
MN_SKMBZ,
MN_SKT,
-- Input/output instructions
MN_EXT,
MN_XAS);
end t400_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_pack-p.vhd,v $
-- Revision 1.3 2006/05/27 19:16:52 arniml
-- interrupt functionality added
--
-- Revision 1.2 2006/05/22 00:01:21 arniml
-- operations for IN port added
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The Program memory controller.
--
-- $Id: t400_pmem_ctrl-c.vhd,v 1.1.1.1 2006/05/06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_pmem_ctrl_rtl_c0 of t400_pmem_ctrl is
for rtl
end for;
end t400_pmem_ctrl_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_pmem_ctrl-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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------------------------------------------------------------------------------
--
-- The Program memory controller.
--
-- $Id: t400_pmem_ctrl.vhd,v 1.3 2006/05/28 15:32:40 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_pmem_ctrl is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
a_i : in dw_t;
m_i : in dw_t;
-- Control Interface ------------------------------------------------------
op_i : in pc_op_t;
dec_data_i : in dec_data_t;
-- Stack Interface --------------------------------------------------------
pc_o : out pc_t;
pc_i : in pc_t;
-- Program Memory Interface -----------------------------------------------
pm_addr_o : out pc_t
);
end t400_pmem_ctrl;
library ieee;
use ieee.numeric_std.all;
-- pragma translate_off
use work.tb_pack.tb_pc_s;
-- pragma translate_on
architecture rtl of t400_pmem_ctrl is
signal pc_q : pc_t;
signal last_pc_s : pc_t;
begin
-----------------------------------------------------------------------------
-- Determine last program counter address
-----------------------------------------------------------------------------
last_pc_s <= to_unsigned(16#1ff#, pc_t'length)
when opt_type_g = t400_opt_type_410_c else
to_unsigned(16#3ff#, pc_t'length);
-----------------------------------------------------------------------------
-- Process pc
--
-- Purpose:
-- Implements the program counter.
--
pc: process (ck_i, por_i)
begin
if por_i then
pc_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
pc_q <= (others => '0');
elsif ck_en_i then
-- determine PC update mode
case op_i is
-- increment program counter ----------------------------------------
when PC_INC_PC =>
if pc_q = last_pc_s then
-- roll over
pc_q <= (others => '0');
else
pc_q <= pc_q + 1;
end if;
-- Load lower 6 bits from program memory data -----------------------
when PC_LOAD_6 =>
pc_q(5 downto 0) <= unsigned(dec_data_i(5 downto 0));
-- Load lower 7 bits from program memory data -----------------------
when PC_LOAD_7 =>
pc_q(6 downto 0) <= unsigned(dec_data_i(6 downto 0));
-- Load lower 8 bits from program memory data -----------------------
when PC_LOAD_8 =>
pc_q(7 downto 0) <= unsigned(dec_data_i(7 downto 0));
-- Load all bits from program memory data ---------------------------
when PC_LOAD =>
pc_q <= unsigned(dec_data_i);
-- pop program counter from stack -----------------------------------
when PC_POP =>
pc_q <= pc_i;
-- update program counter for LQID instruction ----------------------
when PC_LOAD_A_M =>
pc_q(7 downto 4) <= unsigned(a_i);
pc_q(3 downto 0) <= unsigned(m_i);
-- load interrupt vector --------------------------------------------
when PC_INT =>
if opt_type_g = t400_opt_type_420_c then
-- load address 0x100, i.e. skip first instruction at
-- vector address 0x0ff which has to be a NOP :-)
pc_q <= (8 => '1', others => '0');
end if;
when others =>
null;
end case;
end if;
end if;
end process pc;
--
-----------------------------------------------------------------------------
-- pragma translate_off
-- instrument interrupt testbench
tb_pc_s <= pc_q;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
pc_o <= pc_q;
pm_addr_o <= pc_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_pmem_ctrl.vhd,v $
-- Revision 1.3 2006/05/28 15:32:40 arniml
-- load 0x100 upon interrupt
--
-- Revision 1.2 2006/05/27 19:16:52 arniml
-- interrupt functionality added
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The reset generation unit.
--
-- $Id: t400_reset-c.vhd,v 1.1.1.1 2006/05/06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_reset_rtl_c0 of t400_reset is
for rtl
end for;
end t400_reset_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_reset-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The reset generation unit.
--
-- $Id: t400_reset.vhd,v 1.1.1.1 2006/05/06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t400_reset is
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
icyc_en_i : in boolean;
por_i : in boolean;
-- Reset Interface --------------------------------------------------------
reset_n_i : in std_logic;
res_o : out boolean
);
end t400_reset;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_reset is
type res_state_t is (IDLE,
RES1, RES2,
RES_ACTIVE);
signal res_state_q : res_state_t;
signal res_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process res_fsm
--
-- Purpose:
-- Implements the reset timing/controlling FSM.
-- User's Guide chapter 2.3 requires that reset_n_i has to be low for
-- at least 3 instruction cycle times until it initializes the CPU.
--
res_fsm: process (ck_i, por_i)
begin
if por_i then
res_state_q <= IDLE;
res_q <= false;
elsif ck_i'event and ck_i = '1' then
res_q <= false;
if icyc_en_i then
case res_state_q is
when IDLE =>
if reset_n_i = '0' then
res_state_q <= RES1;
end if;
when RES1 =>
if reset_n_i = '0' then
res_state_q <= RES2;
else
res_state_q <= IDLE;
end if;
when RES2 =>
if reset_n_i = '0' then
res_state_q <= RES_ACTIVE;
else
res_state_q <= IDLE;
end if;
when RES_ACTIVE =>
res_q <= true;
if reset_n_i = '1' then
res_state_q <= IDLE;
end if;
when others =>
res_state_q <= IDLE;
end case;
end if;
end if;
end process res_fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
res_o <= res_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_reset.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The serial input/output unit.
--
-- $Id: t400_sio-c.vhd,v 1.1.1.1 2006/05/06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_sio_rtl_c0 of t400_sio is
for rtl
end for;
end t400_sio_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_sio-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The serial input/output unit.
--
-- $Id: t400_sio.vhd,v 1.3 2006/05/07 02:24:16 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.all;
use work.t400_opt_pack.all;
entity t400_sio is
generic (
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
phi1_i : in std_logic;
out_en_i : in boolean;
in_en_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in sio_op_t;
en0_i : in std_logic;
en3_i : in std_logic;
-- SIO Interface ----------------------------------------------------------
a_i : in dw_t;
c_i : in std_logic;
sio_o : out dw_t;
-- Pad Interface ----------------------------------------------------------
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end t400_sio;
library ieee;
use ieee.numeric_std.all;
use work.t400_io_pack.all;
architecture rtl of t400_sio is
signal si_q : std_logic;
type si_flt_t is (SI_LOW_0, SI_LOW_1,
SI_HIGH_0, SI_HIGH_1);
signal si_flt_s,
si_flt_q : si_flt_t;
signal si_0_ok_s,
si_1_ok_s : boolean;
signal si_0_ok_q,
si_1_ok_q : boolean;
signal dec_sio_s : boolean;
signal new_sio_s,
sio_q : unsigned(dw_range_t);
signal skl_q : std_logic;
signal phi1_en_q : std_logic;
signal so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements.
--
seq: process (ck_i, por_i)
begin
if por_i then
sio_q <= (others => '0');
skl_q <= '1';
phi1_en_q <= '1';
si_q <= '1';
si_flt_q <= SI_LOW_0;
si_0_ok_q <= false;
si_1_ok_q <= false;
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
skl_q <= '1';
phi1_en_q <= '1';
else
if in_en_i then
-- sample asynchronous SI input
si_q <= si_i;
end if;
if out_en_i then
-- SI filter FSM
si_flt_q <= si_flt_s;
-- SI low/high markers
si_0_ok_q <= si_0_ok_s;
si_1_ok_q <= si_1_ok_s;
end if;
-- SIO shift register / counter
if op_i = SIO_LOAD and ck_en_i then
-- parallel update has priority
sio_q <= unsigned(a_i);
skl_q <= c_i;
else
sio_q <= new_sio_s;
end if;
if ck_en_i then
-- delay enable of PHI1 by one clock cycle
-- this prevents glitches on sk_o when enabling/disabling
-- sk_o as a clock output
phi1_en_q <= skl_q;
end if;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process new_sio
--
-- Purpose:
-- Calculates the new value of SIO.
-- Splitting this from the sequential process is required to deliver
-- the transient new value of SIO to sio_o upon reading SIO.
--
new_sio: process (out_en_i,
en0_i,
sio_q,
si_q,
dec_sio_s)
begin
-- default value
new_sio_s <= sio_q;
if out_en_i then
if en0_i = '0' then
-- shift register mode
new_sio_s(3 downto 1) <= sio_q(2 downto 0);
new_sio_s(0) <= si_q;
else
-- counter mode
if dec_sio_s then
new_sio_s <= sio_q - 1;
end if;
end if;
end if;
end process new_sio;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process si_sample
--
-- Purpose:
-- Implements the low pass filter on SI for low and high levels.
--
si_sample: process (si_q,
si_flt_q,
si_0_ok_q, si_1_ok_q)
begin
-- default assignments
si_flt_s <= si_flt_q;
si_0_ok_s <= si_0_ok_q;
si_1_ok_s <= si_1_ok_q;
dec_sio_s <= false;
case si_flt_q is
when SI_LOW_0 =>
if si_q = '0' then
si_flt_s <= SI_LOW_1;
else
si_flt_s <= SI_HIGH_0;
end if;
when SI_LOW_1 =>
if si_q = '0' then
si_0_ok_s <= true; -- enough '0' on SI
if not si_0_ok_q and si_1_ok_q then
-- decrement counter if durations of high and low phases
-- were long enough
dec_sio_s <= true;
end if;
else
si_flt_s <= SI_HIGH_0;
si_1_ok_s <= false; -- restart measuring
end if;
when SI_HIGH_0 =>
si_1_ok_s <= false; -- restart marker
if si_q = '1' then
si_flt_s <= SI_HIGH_1;
else
si_flt_s <= SI_LOW_0;
end if;
when SI_HIGH_1 =>
if si_q = '1' then
si_1_ok_s <= true; -- enough '1' on SI
else
si_flt_s <= SI_LOW_0;
si_0_ok_s <= false; -- restart measuring
end if;
when others =>
null;
end case;
end process si_sample;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
sio_o <= std_logic_vector(new_sio_s);
so_s <= en3_i and (en0_i or sio_q(3));
sk_s <= phi1_en_q and (en0_i or phi1_i);
so_o <= io_out_f(dat => so_s, opt => opt_so_output_type_g);
so_en_o <= io_en_f (en => vdd_s,
dat => so_s, opt => opt_so_output_type_g);
sk_o <= io_out_f(dat => sk_s, opt => opt_sk_output_type_g);
sk_en_o <= io_en_f (en => vdd_s,
dat => sk_s, opt => opt_sk_output_type_g);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_sio.vhd,v $
-- Revision 1.3 2006/05/07 02:24:16 arniml
-- fix sensitivity list
--
-- Revision 1.2 2006/05/06 13:34:58 arniml
-- phi1_en_q is dedicated enable for PHI1 clock to suppress glitches on sk_o
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The skip unit.
-- Skip conditions are checked here and communicated to the decoder unit.
--
-- $Id: t400_skip-c.vhd,v 1.1.1.1 2006/05/06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_skip_rtl_c0 of t400_skip is
for rtl
end for;
end t400_skip_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_skip-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The skip unit.
-- Skip conditions are checked here and communicated to the decoder unit.
--
-- $Id: t400_skip.vhd,v 1.5 2006/06/05 14:20:34 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_skip is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in skip_op_t;
dec_data_i : in dec_data_t;
carry_i : in std_logic;
c_i : in std_logic;
bd_i : in dw_t;
is_lbi_i : in boolean;
skip_o : out boolean;
skip_lbi_o : out boolean;
-- Data Interface ---------------------------------------------------------
a_i : in dw_t;
m_i : in dw_t;
g_i : in dw_t;
tim_c_i : in boolean
);
end t400_skip;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_skip is
signal skip_q,
skip_next_q : boolean;
signal skip_lbi_q : boolean;
signal skip_int_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process skip
--
-- Purpose:
-- Implements the skip logic.
--
skip: process (ck_i, por_i)
variable t420_type_v : boolean;
begin
if por_i then
skip_next_q <= false;
skip_q <= false;
skip_lbi_q <= false;
skip_int_q <= false;
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
skip_next_q <= false;
skip_q <= false;
skip_lbi_q <= false;
skip_int_q <= false;
elsif ck_en_i then
t420_type_v := opt_type_g = t400_opt_type_420_c;
if ck_en_i then
case op_i is
-- update skip information ----------------------------------------
when SKIP_UPDATE =>
skip_q <= skip_next_q;
-- also reset skip_next flag
skip_next_q <= false;
-- reset skip-on-lbi flag when this was not an LBI
if not is_lbi_i then
skip_lbi_q <= false;
end if;
-- skip always ----------------------------------------------------
when SKIP_NOW =>
skip_next_q <= true;
-- skip on carry --------------------------------------------------
when SKIP_CARRY =>
skip_next_q <= carry_i = '1';
-- skip on C ------------------------------------------------------
when SKIP_C =>
skip_next_q <= c_i = '1';
-- skip on BD underflow ------------------------------------------
when SKIP_BD_UFLOW =>
skip_next_q <= unsigned(bd_i) = 15;
-- skip on BD overflow -------------------------------------------
when SKIP_BD_OFLOW =>
skip_next_q <= unsigned(bd_i) = 0;
-- skip on LBI instruction ----------------------------------------
when SKIP_LBI =>
skip_lbi_q <= true;
-- skip on A and M equal ------------------------------------------
when SKIP_A_M =>
skip_next_q <= unsigned(a_i) = unsigned(m_i);
-- skip on G zero -------------------------------------------------
when SKIP_G_ZERO =>
skip_next_q <= unsigned(g_i) = 0;
-- skip on G bit --------------------------------------------------
when SKIP_G_BIT =>
skip_next_q <= unsigned(g_i and dec_data_i(dw_range_t)) = 0;
-- skip on M bit --------------------------------------------------
when SKIP_M_BIT =>
skip_next_q <= unsigned(m_i and dec_data_i(dw_range_t)) = 0;
-- skip on timer carry --------------------------------------------
when SKIP_TIMER =>
skip_next_q <= tim_c_i;
null;
-- push skip state when vectoring to interrupt routine ------------
when SKIP_PUSH =>
if t420_type_v then
-- save next skip flag
skip_int_q <= skip_next_q;
skip_next_q <= false;
-- never skip first instruction of interrupt routine
skip_q <= false;
end if;
-- pop skip state for RET from interrupt routine ------------------
when SKIP_POP =>
if t420_type_v then
-- push'ed info must be pop'ed to skip_next_q as pop'ing
-- happens during RET of interrupt routine
-- skip info is valid for next instruction
skip_next_q <= skip_int_q;
skip_int_q <= false;
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process skip;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
skip_o <= skip_q;
skip_lbi_o <= skip_lbi_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_skip.vhd,v $
-- Revision 1.5 2006/06/05 14:20:34 arniml
-- interface comments added
--
-- Revision 1.4 2006/05/28 15:35:33 arniml
-- fix pop'ing of skip flag
--
-- Revision 1.3 2006/05/27 19:16:52 arniml
-- interrupt functionality added
--
-- Revision 1.2 2006/05/20 02:47:52 arniml
-- skip-on-timer implemented
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

28
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-------------------------------------------------------------------------------
--
-- The stack unit.
--
-- $Id: t400_stack-c.vhd,v 1.1.1.1 2006/05/06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_stack_rtl_c0 of t400_stack is
for rtl
end for;
end t400_stack_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_stack-c.vhd,v $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The stack unit.
--
-- $Id: t400_stack.vhd,v 1.3 2006/06/11 02:12:11 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_stack is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
-- Stack Control Interface ------------------------------------------------
op_i : in stack_op_t;
-- Program Counter Interface ----------------------------------------------
pc_i : in pc_t;
pc_o : out pc_t
);
end t400_stack;
-- pragma translate_off
use work.tb_pack.tb_sa_s;
-- pragma translate_on
architecture rtl of t400_stack is
signal sa_q,
sb_q,
sc_q : pc_t;
begin
-----------------------------------------------------------------------------
-- Process stack
--
-- Purpose:
-- Implements the stack consisting of SA, SB, SC.
-- SC is skipped when it's a 41xL.
--
stack: process (ck_i, por_i)
variable t41x_type_v : boolean;
begin
if por_i then
sa_q <= (others => '0');
sb_q <= (others => '0');
sc_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
-- determine type
t41x_type_v := opt_type_g = t400_opt_type_410_c;
if ck_en_i then
case op_i is
when STACK_PUSH =>
sa_q <= pc_i;
sb_q <= sa_q;
if not t41x_type_v then
sc_q <= sb_q;
else
sc_q <= (others => '0');
end if;
when STACK_POP =>
sa_q <= sb_q;
if not t41x_type_v then
sb_q <= sc_q;
end if;
when others =>
null;
end case;
end if;
end if;
end process stack;
--
-----------------------------------------------------------------------------
-- pragma translate_off
-- instrument interrupt testbench
tb_sa_s <= sa_q;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
pc_o <= sa_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_stack.vhd,v $
-- Revision 1.3 2006/06/11 02:12:11 arniml
-- assign sc_q with 0 for t41x derivatives
-- this prevents a dummy warning about inferring latches for sc_q
--
-- Revision 1.2 2006/05/27 19:15:59 arniml
-- instrument testbench
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The timer unit.
--
-- $Id: t400_timer-c.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_timer_rtl_c0 of t400_timer is
for rtl
end for;
end t400_timer_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_timer-c.vhd,v $
-- Revision 1.1.1.1 2006/06/10 17:50:15 arnim
-- copied from opencores.org repository, pre-1.0 release on 10-Jun-2006
--
-- Revision 1.1 2006/05/20 02:47:12 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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-------------------------------------------------------------------------------
--
-- The timer unit.
--
-- $Id: t400_timer.vhd,v 1.1.1.1 2006/06/10 17:50:15 arnim Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.all;
entity t400_timer is
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
icyc_en_i : in boolean;
-- Skip Interface ---------------------------------------------------------
op_i : in skip_op_t;
c_o : out boolean
);
end t400_timer;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_timer is
signal cnt_q : unsigned(9 downto 0);
signal c_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements:
-- * timer counter
-- * carry (underflow) marker flag
--
seq: process (ck_i, por_i)
begin
if por_i then
cnt_q <= (others => '1');
c_q <= false;
elsif ck_i'event and ck_i = '1' then
if icyc_en_i then
if cnt_q = 0 then
-- counter underflow:
-- * reload counter
-- * set marker flag
cnt_q <= (others => '1');
c_q <= true;
else
cnt_q <= cnt_q - 1;
end if;
end if;
if ck_en_i and op_i = SKIP_TIMER then
c_q <= false;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
c_o <= c_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: t400_timer.vhd,v $
-- Revision 1.1.1.1 2006/06/10 17:50:15 arnim
-- copied from opencores.org repository, pre-1.0 release on 10-Jun-2006
--
-- Revision 1.1 2006/05/20 02:47:12 arniml
-- initial check-in
--
-------------------------------------------------------------------------------

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GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Everyone is permitted to copy and distribute verbatim copies
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Preamble
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0. This License applies to any program or other work which contains
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END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) 19yy <name of author>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) 19yy name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Library General
Public License instead of this License.

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README for the T48 uController project
======================================
Version: $Date: 2005/06/19 15:59:48 $
Introduction
------------
The T48 µController core is an implementation of the MCS-48 microcontroller
family architecture. While being a controller core for SoC, it also aims for
code-compatability and cycle-accuracy so that it can be used as a drop-in
replacement for any MCS-48 controller.
It can be configured to better suit the requirements and characteristics of
the integrating system. On the other hand, nearly the full functionality of a
stock 8048/8049 is available.
Download
--------
Download the latest stable release from the project homepage at OpenCores.org:
http://www.opencores.org/projects.cgi/web/t48/overview/
You can get the latest version of the design files from CVS:
http://www.opencores.org/pdownloads.cgi/list/t48
Please keep in mind that this is work in progress and might contain smaller or
bigger problems.
You should also check the Tracker for known bugs and see if they affect your
work.
Installation
------------
Once the directory structure is generated either by check-out from CVS or by
unpacking the tar-archive, the central project initialization file should be
set up. A template called init_project.template.sh is located in the sw
directory where a copy can be edited. Normally, only the definition for the
variable PROJECT_DIR has to be adjusted to the path where the directory
structure is located.
The commands for setting the necessary variables assume a bash/sh-like
shell. In case you run a different shell like csh or ksh, you should adjust
these commands as well.
The meaning of the variables is as follows:
* PROJECT_DIR
Points to the root of the project installation. All further references are
derived from its setting.
* VERIF_DIR
Location of the verification suite.
* SIM_DIR
Directory for running simulations.
These variables must be properly set whenever scripts or makefiles of the T48
project are executed. Otherwise, you will most likely encounter error
messages.
NOTE: The concepts of the mentioned shells require that the init_project.sh is
run in the context of the shell. I.e. you should 'source' the script
instead of executing it like a command. This will make sure that the
variable settings are really effective in the calling shell instance.
Directory Structure
-------------------
The project's directory structure follows the proposal of OpenCores.org.
t48
|
\--+-- rtl
| |
| \-- vhdl : VHDL code containing the RTL description
| | of the core.
| \-- system : RTL VHDL code of sample systems.
|
+-- bench
| |
| \-- vhdl : VHDL testbench code.
|
+-- sim
| |
| \-- rtl_sim : Directory for running simulations.
|
\-- sw : General purpose scripts and files.
|
+-- i8039emu : An MCS-48 emulator written in C.
|
\-- verif : The verification suite.
|
+-- include : Global includes and makefiles.
|
+-- black_box : Black-box verification tests.
|
+-- white_box : White-box verification tests.
|
\-- gp_sw : General purpose software.
Compiling the VHDL Code
-----------------------
VHDL compilation and simulation tasks take place inside in sim/rtl_sim
directory. The project setup supports only the batch mode of certain
simulators. However, there should be no problems to integrate the testbench
and RTL code into arbitrary simulation environments.
The main file for compilation is Makefile.hier which contains all information
regarding the dependencies of the source files and their compilation
order. There is a dedicated file for each supported simulator that maps the
generic information of Makefile.hier to object files specific to the given
simulator.
Compilation is based on the make-utility, thus invocation looks like this:
$ make -f Makefile.<simulator>
where <simulator> denotes one of the supported simulators:
* Makefile.ghdl
Tristan Gingold's GHDL simulator/compiler, a VHDL front-end for gcc.
http://ghdl.free.fr/
* Makefile.simili
VHDL Simili, a VHDL simulator by Symphony EDA
http://www.symphonyeda.com/
Make will analyze all VHDL files (RTL and testbench code) and elaborate all
three testbench top-levels if appropriate for the chosen simulator:
* tb_behav_c0
The main testbench for regression testing.
Instantiates the plain t48_core and provides internal RAM (256 bytes) and
ROM (2k bytes) plus 2k bytes of external ROM.
* tb_t8048_behav_c0
The testbench for the t8048 sample system.
* tb_t8039_behav_c0
The testbench for the 8039 sample system.
Each Makefile has a 'clean' target to delete all intermediate data:
$ make -f Makefile.<simulator> clean
The basic simple sequence list can be found in COMPILE_LIST. This can be
useful to quickly set up the analyze stage of any compiler or
synthesizer. Especially when synthesizing the code, you want to skip the VHDL
configurations in *-c.vhd and everything below the bench/ directory.
Preparation of the ROM Files
----------------------------
All testbenches listed above need two files in hex-format. They contain the
program for the T48 core and are loaded into internal and external ROM at
simulation startup. Their existance is mandatory as they are referenced in the
VHDL code of the ROM model lpm_rom.vhd. In case they are missing, the
simulation will stop immediately after elaborating the design.
These files are:
* t48_rom.hex
Internal ROM contents at address range 000H to 7FFH.
Intel hex format, starting at address 000H.
* t48_ext_rom.hex
External ROM contents at address range 800H to FFFH.
Intel hex format, starting at address 000H.
The verification flow for the T48 project generates these two files
automatically from the assembler source files.
All regression tests and the general purpose software is organized in a cell
structure. Currently, this means that the software for a cell is contained in
a dedicated directory where the assembler run takes place. In the future,
there will be more aspects to a cell.
Assembling, linking and putting the hex-files in place is under the control of
the make-mechanism. E.g. to assemble the source code of a cell, issue the
following command:
$ make -f $VERIF_DIR/include/Makefile.cell
This generates the linker file (test.p) and distributes its contents to the
required ROM files for internal and external program ROM. The target 'simu'
copies these files automatically to the simulation directory. So most likely,
for running a test case or any other software, you will want to issue:
$ make -f VERIF_DIR/include/Makefile.cell simu clean
The only supported assembler is Alfred Arnold's macroassembler AS. See
http://john.ccac.rwth-aachen.de:8000/as/
Verification Environment
------------------------
The verification environment consists of a number of test programs. They are
all self-checking. I.e. after testing the targeted functionality, they emit a
pass/fail information. This information is detected by the testbench which
stops the simulation and prints out the simulation result. This is the default
mechanism for stopping the VHDL simulation.
Pass/fail is signalled by a certain sequence of the accumulator contents:
1) Accumulator contains AAH
2) Accumulator contains 55H
3) Accumulator contains 01H -> Pass
Accumulator contains 00H -> Fail
The detection is modelled like a state machine and in case the sequence is of
bytes inside the accumulator does not match, the detection process restarts
from the beginning. This mechanism is part of all verification tests.
The complete regression suite can be executed with the run_regression.pl
script. For each test cell, it steps through the sequence
1) Assemble the source code
2) Run the compiled VHDL design (currently only GHDL)
3) Optionally perform a dump compare against the C-model
It is highly recommended to redirect the output of run_regression.pl into a
file. Otherwise, analyzing the messages related to each test cell is almost
impossible.

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-------------------------------------------------------------------------------
--
-- The Arithmetic Logic Unit (ALU).
-- It contains the ALU core plus the Accumulator and the Temp Reg.
--
-- $Id: alu-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t48_alu_rtl_c0 of t48_alu is
for rtl
end for;
end t48_alu_rtl_c0;

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